US 6,272,068 B1 · Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis

Abstract

Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.

Claims14

Dependent claims

A double data rate synchronous DRAM integrated circuit, comprising:

a first buffer for changing the voltage level of an external clock signal;
a pulse generator for receiving as input the output of the first buffer, generating a pulse at the rising edge of the external clock signal, and outputting the pulse as an internal clock signal;
a first logic circuit for receiving as input a single data rate mode signal input from the outside and the internal clock signal, and generating a data strobe clock signal;
a second buffer for receiving as input an external data strobe signal and the single data rate mode signal, and changing the voltage level of the external data strobe signal in response to the single data rate mode signal;
and
a second logic circuit for receiving as input the output of the second buffer and the data strobe clock signal and generating an internal data strobe signal.

3 more elements

A double data rate synchronous DRAM integrated circuit, comprising:

a buffer for inputting a clock signal;
a logic portion for generating first and second control signals by receiving as input the output of the buffer and a single data rate mode signal, outputting the first and second control signals in response to the clock signal when the single data rate mode signal is deactivated, and activating the first control signal and deactivating the second control signal when the single data rate mode signal is activated;
and
a controlling portion for receiving as input first and second data, not outputting the first and second data when both the first and second control signals are deactivated, outputting only the first data when only the first control signal is activated, and outputting the first and second data when both the first and second control signals are activated.

1 more element

Dependencies are inferred from the claim text.

Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis

Life of this patent

Integrated circuit memory devices that utilize data masking techniques to facilitate test mode analysis

Life of this patent

Abstract

Claims14