SRAM synchronized with an optimized clock signal based on a delay and an external clock

A method for designing an SRAM chip synchronizable with a periodic external clock signal, comprising:

• designing a preliminary architecture of an SRAM chip having peripheral circuits and a plurality of memory cells;
• determining a critical PC time which is the interval of time needed for a worst-case PC scenario operation that requires the most time to execute during the PC phase;
• determining a critical AC time which is the interval of time needed for a worst-case AC scenario operation that requires the most time to execute during the AC phase;
• determining an optimization factor which is the number of times the critical AC time added to the critical PC time can go into the period of an external clock cycle;
• creating an optimization circuit useful to receive a clock signal as an input and output an optimized clock signal that transitions from its high state to its low state a number of times equal to the optimization factor times the number of times the external clock transitions from its high state to its low state, the optimized clock signal remaining in its active states for at least the critical PC time and its inactive state for at least the critical AC time;
• designing the final architecture for the SRAM chip, the final architecture including the plurality of memory cells, the peripheral circuits and the optimization circuit.

An SRAM chip synchronized with an external periodic signal, comprising:

• a memory array having a plurality of memory cells and a plurality of bit lines operably connected with the plurality of memory cells;
• control circuitry, operably connected with the memory array, regulating the operation of the memory cells, and being characterized by a control time equal to the interval of time the control circuitry requires to complete its most time-consuming operation;
• an address decoder, operably connected with the memory array, selecting a single set of memory cells within the memory array, and being characterized by an address time equal to the interval of time the address decoder requires to complete its most time-consuming operation;
• pre-charge circuitry, operably connected with the memory array, charging the bit lines of the memory array to a predetermined state, and being characterized by a pre-charge time equal to the interval of time the pre-charge circuitry requires to complete its most time-consuming operation;
• read circuitry, operably connected with the bit lines of the memory array, receiving signals from the memory cells within the memory array, and being characterized by a read time equal to the interval of time the read circuitry requires to complete its most time-consuming operation;
• write circuitry, operably connected with the bit lines of the memory array, replacing the signals stored by the memory cells within the memory array, being characterized by a write time equal to the interval of time the write circuitry requires to complete its most time-consuming operation;
• and
• a signal optimizer, operably connected with the control circuits, address decoder, pre-charge circuitry, read circuitry and write circuitry, receiving the external periodic signal, and transforming the external periodic signal into a signal that transitions from a high state to a low state a greater number of times than the external periodic signal that maintains its active states for at least a critical PC time and its inactive state for at least a critical AC time, the critical PC time being equal to either the control time, the address time, or the pre-charge time, whichever is larger, and the critical AC time being equal to either the write time, or the read time, whichever is larger.