Synchronous semiconductor memory device capable of high speed reading and writing
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
An address input is received earlier than data input, and a result of decoding of a column address at the time of writing and results of substitution determination for a redundancy memory column are held in a latch circuit corresponding to each bank. When the data anives at the bank, the data is immediately written to each bank, utilizing the results of address processing. Operation frequency of the chip is not limited by the conventionally experienced wasteful wait time for the data in the process of writing, and efficient data input/output is possible.
Claims17
A synchronous semiconductor memory device receiving an address signal in synchronization with a clock signal and inputting/outputting data, comprising:
- a memory array having a plurality of memory cells arranged in a matrix of rows and columns;
- and
- a holding circuit holding positional information corresponding to an address designated by said address signal for specifying a memory cell to which said data is to be written;
- wherein
- a time point when a logic state of said clock signal makes a transition is referred to as a clock edge;
- and
- said holding circuit holds said positional information until said data corresponding to said positional information is input at a second clock edge later than a first clock edge at which said address is input.
A synchronous semiconductor memory device receiving an address signal in synchronization with a clock signal and inputting/outputting data, comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns;
- a logic converting circuit receiving and performing a logic operation on an address designated by said address signal and outputting positional information specifying a memory cell to which said data is to be written;
- and
- a holding circuit holding said positional information.
Dependencies are inferred from the claim text.