Address generating and decoding circuit for use in burst-type random access memory device having a double data rate, and an address generating method thereof

A burst-type random access memory device having a memory cell array for storing data and having a double data rate scheme in which at least two data is inputted/outputted to/from the memory device during a clock cycle, the memory device comprising:

• an address buffer for receiving an externally applied initial address;
• an address generator for generating first addresses in response to the initial address from the address buffer, wherein the first addresses corresponds to a first half period of the clock cycle during a burst mode of operation, respectively;
• and
• a second address generator for generating second addresses in response to the first addresses,
• wherein the second address generator comprises:
• an address incrementor for receiving remaining address bits of a first address except a least significant bit and incrementing a value of the remaining address bits by one to output the incremented address bits as a third address, wherein the remaining address bits correspond to the incremented address bits, respectively;
• a select signal generator for generating select signals in response to burst information signals and the least significant bit of the first address, wherein the select signals correspond to the incremented address bits, respectively;
• and
• a selector for receiving the remaining address bits and the incremented address bits, wherein the selector chooses one of corresponding address bits of the first and the third address in response to the select signals and outputs the chosen address bits as a second address.

A method of generating an address for a burst mode of operation in a burst-type random access memory device having a double data rate scheme in which at least two data is inputted/outputted to/from the random access memory device during a clock cycle, the method comprising the steps of:

• receiving a first address as an initial address from the exterior;
• generating select signals in response to burst information signals and a least significant bit of the first address;
• receiving remaining address bits of the initial address except the least significant bit and incrementing a value of the remaining address bits by one to output the incremented address bits as a second address;
• and
• receiving the remaining address bits the incremented address bits and choosing one of corresponding address bits of the first and the second address in response to the select signals to output the chosen address bits as a next address of the initial address.