Memory with combined synchronous burst and bus efficient functionality

A method of operating an integrated memory circuit selectively operable in a synchronous operational mode and a bus efficient operational mode, the method comprising:

• selecting one of the synchronous operational mode and the bus efficient operational mode in response to an externally provided control signal, the selectable operational modes both supporting read and write operations;
• selecting, as a function of the selected operational mode, one of a plurality of address propagation paths of the integrated memory circuit and one of a plurality of data propagation paths of the integrated memory circuit, such that
• if the synchronous operational mode is selected, externally provided data is synchronized with a corresponding memory address, and
• if the bus efficient operational mode is selected, the externally provided data lags the corresponding memory address.

A method of operating an integrated memory circuit selectively operable in a synchronous operational mode and a bus efficient operational mode, the method comprising:

• selecting one of the synchronous operational mode and the bus efficient operational mode in response to an externally provided control signal, the selectable operational modes both supporting read and write operations;
• if the synchronous operational mode is selected,
• coupling an externally provided address to a memory array through a first address register path having a first address propagation time, and
• coupling externally provided data to the memory array through a first data register path having a first data propagation time;
• and
• if the bus efficient operational mode is selected,
• coupling an externally provided address to the memory array through the first address register path and externally provided data to the memory array through the first data register path during a bus efficient read operation,
• coupling an externally provided address to the memory array through a second address register path having a second address propagation time greater than the first address propagation time during a bus efficient write operation,
• coupling externally provided data to the memory array through a second data register path having a second data propagation time greater than the first data propagation time during a write operation performed in a non-pipelined mode,
• coupling externally provided data to the memory array through the first data register path after a write operation performed in a pipelined mode, and
• coupling externally provided data to the memory array through the second data register path after a read operation performed in the pipelined mode.

A method of operating an integrated memory circuit, the method comprising:

• selecting a first one of a plurality of address propagation paths of the integrated memory circuit when the integrated memory circuit is operating in a synchronous operational mode, the synchronous operational mode supporting both read and write operations;
• selecting the first one of the plurality of address propagation paths when the integrated memory circuit is performing a read operation while operating in a bus efficient operational mode, the bus efficient operational mode supporting both read and write operations;
• selecting a second one of the plurality of address propagation paths when the integrated memory circuit is performing a write operation while operating in the bus efficient operational mode, the second one of the plurality of address propagation paths having a propagation time longer than a propagation time of the first one of the plurality of address propagation paths;
• selecting a first one of a plurality of data propagation paths of the integrated memory circuit when the integrated memory circuit is operating in the synchronous operational mode;
• selecting a second one of the plurality of data propagation paths when the integrated memory circuit is operating in a non-pipelined bus efficient operational mode, the second one of the plurality of data propagation paths having a propagation time longer than a propagation time of the first one of the plurality of data propagation paths;
• and
• selecting one of the first and second ones of the plurality of data propagation paths when the integrated memory circuit is operating in a pipelined bus efficient operational mode, the first data propagation path being selected following a write operation.

A method of operating an integrated memory circuit selectively operable in a synchronous operational mode and a bus efficient operational mode, the method comprising:

• selecting one of the synchronous operational mode and the bus efficient operational mode in response to an externally provided control signal, the selectable operational modes both supporting read and write operations;
• if the synchronous operational mode is selected,
• coupling an externally provided address to a memory array through a first address register path having a first address propagation time, and
• coupling externally provided data to the memory array through a first data register path having a first data propagation time;
• and
• if the bus efficient operational mode is selected,
• coupling an externally provided address to the memory array through the first address register path during a bus efficient read operation,
• coupling an externally provided address to the memory array through a second address register path having a second address propagation time greater than the first address propagation time during a bus efficient write operation,
• coupling externally provided data to the memory array through a second data register path having a second data propagation time greater than the first data propagation time during a bus efficient non-pipelined operation,
• coupling externally provided data to the memory array through the first data register path during a bus efficient pipelined operation after a write operation, and
• coupling externally provided data to the memory array through the second data register path during a bus efficient pipelined operation after a read operation.