US 6,272,060 B1 · Shift register clock scheme

Abstract

A shift register system is disclosed wherein shift registers buffering memory data perform shift operations in response to a set of sub-clock signals. The set of sub-clock signals comprise nested sub-clock signals having non-overlapping transitions formed from a system clock signal or power on reset signal. Each shift register (or bank of shift registers) responds to a different sub-clock signal. As a result, shift operations are spread out over a period of time rather than occurring simultaneously. Thus, the current drawn during each shift operation is similarly spread out over a period of time. The maximum current drawn during any one shift operation is inversely proportional to the number of non-overlapping sub-clock signal. Therefore, the maximum current drawn (i.e., current spike) drawn during memory operations is minimized.

Claims17

Dependent claims

A memory system comprising:

a first serial-in serial-out shift register receiving a data signal, the first shift register being controlled by a first clock signal;
and
a second serial-in serial-out shift register coupled in series with the first shift register and providing an output data signal, the second shift register being controlled by a second clock signal,
wherein the second clock signal has a rising edge occurring a first time period after a rising edge of the first clock signal and a falling edge occurring a second time period prior to a falling edge of the first clock signal.

1 more element

A memory system comprising:

a clock delay circuit generating a first clock signal, a second clock signal, and a third clock signal, wherein the first, second, and third clock signals are different clock signals;
a first clock phase generation circuit generating a first control clock signal, the first clock phase generation circuit being clocked by the first clock signal;
a first shift register having a first input terminal and a first output terminal, the first shift register being clocked by the first control clock signal;
a second clock phase generation circuit generating a second control clock signal, the second clock phase generation circuit being clocked by the second clock signal;
a second shift register having a second input terminal and a second output terminal, the second input terminal of the second shift register being coupled to the first output terminal of the first shift register, the second shift register being clocked by the second control clock signal;
a third clock phase generation circuit generating a third control clock signal, the third clock phase generation circuit being clocked by the third clock signal;
and
a third shift register having a third input terminal and a third output terminal, the third input terminal of the third shift register being coupled to the second output terminal of the second shift register, the third shift register being clocked by the third control clock signal;
and
a storage memory structure coupled to the first, second, and third output terminals;
wherein a data signal received-at the first input terminal is clocked through the first shift register by the first control clock signal, a data signal received at the second input terminal is clocked through the second shift register by the second control clock signal, and a data signal received at the third input terminal is clocked through the third shift register by the third control clock signal.

8 more elements

Dependencies are inferred from the claim text.

Shift register clock scheme

Life of this patent

Shift register clock scheme

Life of this patent

Abstract

Claims17