Bit line sense-amplifier for a semiconductor memory device and a method for driving the same
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsDouk Hyoun Ryu, Yong Ho Seol
Life of this patent
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Abstract
A bit line sense-amplifier for a semiconductor memory device and a method for driving the same do not apply a bit line precharge voltage by a switch in an equalization operation, perform an equalization operation by interconnecting a plurality of sense-amplifier lines, then perform a precharge operation by applying a bit line precharge voltage through NMOS transistor of the switch, increase a sensing speed by reducing a loading of a sense-amplifier, reduce a transient current, and minimize a power-consumption by performing a precharge operation after a bit line equalization.
Claims10
A bit line sense amplifier for a semiconductor memory device, comprising:
- first and second bit lines respectively having two bit lines, for transmitting a stored data to a memory cell;
- sense-amplifier lines for transmitting a data loaded on the first bit line to a sense-amplifier;
- first and second switch means which are controlled by first and second control signals, and selectively connect two bit lines of the first bit line to the sense-amplifier lines;
- third and fourth switch means which are controlled by third and fourth control signals, and selectively connect two bit lines of the second bit line to the sense-amplifier lines;
- and
- a fifth switch means which is controlled by a fifth control signal, and selectively applies a bit line precharge voltage to the sense-amplifier lines;
- said first, second, third, fourth and fifth switch means being comprised of NMOS transistors having respective gates for receiving said first, second, third, fourth and fifth control signals.
In a semiconductor memory device including:
- first and second bit lines respectively having two bit lines, for transmitting a stored data to a memory cell;
- a sense-amplifier line having two lines, for transmitting a data loaded on the first bit line to a sense-amplifier;
- first switch means for selectively connecting the first bit line to the sense-amplifier line;
- second switch means for selectively connecting the sense-amplifier line to the second bit line;
- and third switch means for selectively applying a bit line precharge voltage to the sense-amplifier line, a method for driving a bit line sense-amplifier, comprising the steps of:
- (a) interconnecting first and second bit lines and sense-amplifier line, and applying a bit line precharge voltage to the sense-amplifier line;
- (b) separating the second bit line from the sense-amplifier line, and separating the sense-amplifier line from the bit line precharge voltage;
- (c) selecting a desired memory cell, and transmitting a data to the bit lines and the sense-amplifier line by a voltage division;
- (d) sensing a data transmitted to the sense-amplifier line by a sense-amplifier, and performing a write-back operation to the selected memory cell;
- (e) performing an equalization by interconnecting two lines of the sense-amplifier line;
- and
- (f) connecting the data lines to the sense-amplifier line, and applying the bit line precharge voltage to the sense-amplifier line.
In a semiconductor memory device including:
- first and second bit lines respectively having two bit lines, for transmitting a stored data to a memory cell;
- a sense-amplifier line having two lines, for transmitting a data loaded on the first bit line to a sense-amplifier;
- first switch means for selectively connecting the first bit line to the sense-amplifier line;
- second switch means for selectively connecting the sense-amplifier line to the second bit line;
- and third switch means for selectively applying a bit line precharge voltage to the sense-amplifier line, a method for driving a bit line sense-amplifier for the semiconductor memory device, comprising the steps of:
- (g) interconnecting first and second bit lines and sense-amplifier line, and applying a bit line precharge voltage to the sense-amplifier line;
- (h) separating the second bit line from the sense-amplifier line, and separating the sense-amplifier line from the bit line precharge voltage;
- (i) selecting a desired memory cell, and transmitting a data to the first bit line and the sense-amplifier line by a voltage division;
- (j) separating the first bit line from the sense-amplifier line;
- (k) sensing a data transmitted to the sense-amplifier line;
- (l) connecting one line of the first bit line connected to the selected cell to one line of the sense-amplifier line, and performing a write-back operation;
- (m) interconnecting two lines of the sense-amplifier line under the condition that one line of the first bit line connected to the selected cell is only connected to one line of the sense-amplifier line, and performing an equalization operation;
- and
- (n) connecting the other line of the first bit line to the other line of the sense-amplifier line, connecting the sense-amplifier line to the second bit line, and applying the bit line precharge voltage to the sense-amplifier line.
In a semiconductor memory device including:
- first and second bit lines respectively having two bit lines, for transmitting a stored data to a memory cell;
- a sense-amplifier line having two lines, for transmitting a data loaded on the first bit line to a sense-amplifier;
- first switch means for selectively connecting the first bit line to the sense-amplifier line;
- second switch means for selectively connecting the sense-amplifier line to the second bit line;
- and third switch means for selectively applying a bit line precharge voltage to the sense-amplifier line, a method for driving a bit line sense-amplifier for the semiconductor memory device, comprising the steps of:
- (o) interconnecting first and second bit lines and sense-amplifier line, and applying a bit line precharge voltage to the sense-amplifier line;
- (p) separating the second bit line from the sense-amplifier line, and separating the sense-amplifier line from the bit line precharge voltage;
- (q) selecting a desired memory cell, and transmitting a data to the first bit line and the sense-amplifier line by a voltage division;
- (r) separating the first bit line from the sense-amplifier line;
- (s) sensing a data transmitted to the sense-amplifier line;
- (t) connecting the first bit line to the sense-amplifier line, and performing a write-back operation to the selected cell;
- (u) interconnecting two lines of the sense-amplifier line, and performing an equalization operation;
- and
- (v) connecting the sense-amplifier line to the second bit line, and applying the bit line precharge voltage to the sense-amplifier line.
A bit line sense amplifier for a semiconductor memory device, comprising:
- a first bit line part having a pair of bit lines, for transmitting data to or from a memory cell;
- a second bit line part having a pair of bit lines, for transmitting data to or from another memory cell;
- a sense-amplifier line part having a pair of bit lines, for transmitting a data from at least one of the first bit line part and the second bit line part into a sense-amplifier, said sense-amplifier line part being connected in series to said first and second bit line parts;
- first and second switch means for connecting said sense-amplifier line part with said first bit line part, each of said first and second switch means being controlled respectively by one of a first control signal and a second control signal;
- third and fourth switch means for connecting said sense-amplifier line part with said second bit line part, each of said third and fourth switch means being controlled respectively by one of a third control signal and a fourth control signal;
- equalization means for equalizing the pair of bit lines of the sense-amplifier line part responsive to an equalizing control signal;
- and
- precharge means for precharging the pair of bit lines of the sense-amplifier line part to a precharge voltage, said precharge means being controlled by a precharge control signal separate from said equalizing control signal.
Dependencies are inferred from the claim text.