Semiconductor memory device

A device for a semiconductor memory having a memory cell array having a plurality of normal memory cells associated with respective normal main word lines and having a redundant row of memory cells associated with a redundant main word line, said device for accessing any of said memory cells by changing one of said associated word lines from a standby state to an active state, said device comprising:

• a plurality of normal row decoders for decoding an input row address data for specifying one of said normal main word lines when access is made to any of said memory cells other than said redundant row of memory cells;
• a redundant row decoder for specifying said redundant main word line when access is made to any memory cell which belongs to said redundant row;
• a decision circuit for determining whether or not to select a memory cell belonging to said redundant row based on said input row address data and selecting said redundant row decoder simultaneous to selecting said memory cell belonging to said redundant row;
• a first controller for rendering said normal main word lines to one of a standby state and an active state and for generating a first control signal for changing said normal main word lines from said active state to said standby state when said decision circuit has determined to select a memory cell belonging to said redundant row and a second control signal for changing said redundant word line to one of said standby state and said active state;
• and
• a second controller for selecting one of said plurality of normal row decoders based on said input row address data and for rendering said normal row decoders to a non-selected state when said decision circuit has determined to select a memory cell belonging to said redundant row.

A device for a semiconductor memory having a memory cell array comprised of a plurality of normal memory cells associated with respective normal main word lines and a redundant row of memory cells associated with a redundant main word line, said device for accessing any of said memory cells by changing an associated word line from a standby state to an active state, said device comprising:

• a plurality of normal row decoders for decoding an input row address data and for specifying one of said normal main word lines when said address data indicates access is made to those of said memory cells which are other than said redundant row of memory cells;
• a redundant row decoder for specifying said redundant main word line when said address data indicates access is made to any memory cell which belongs to said redundant row;
• a decision circuit for determining, based on said input row address data, whether or not to select a memory cell belonging to said redundant row and selecting said redundant row decoder essentially simultaneous to selecting said memory cell belonging to said redundant row;
• a first controller supplying a first control signal for rendering essentially simultaneously both said specified one normal main word line and said redundant main word line to an active state, and supplying subsequently a second control signal for changing only said specified one normal main word line back from said active state to said standby state when said decision circuit has determined to select a memory cell belonging to said redundant row;
• and
• a second controller for selecting one of said plurality of normal row decoders based on said input row address data and rendering said selected normal row decoder to a non-selected state when said decision circuit has determined to select a memory cell belonging to said redundant row.

A semiconductor memory device comprising:

• a normal row decoder for activating a predetermined one of a plurality of normal word lines when an address data is input,
• a redundancy decision circuit for selecting a predetermined one of one or more redundant word lines when said input address data indicates a predetermined redundancy address;
• and
• at least one switch for deactivating said activated normal word line based on an output signal from said redundancy decision circuit.

A semiconductor memory comprising:

• a first array of normal memory cells;
• a second array of redundant memory cells;
• and
• at least one precharging signal for said first array,
• wherein said at least one precharging signal is activated from a standby state to an active state upon receipt of a memory request signal and subsequently changed from said active state back to said standby state upon a determination that said memory request signal involves an address in said second array.