Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device

A semiconductor memory device operating synchronously with a clock signal to transmit and receive a data signal in response to an address signal and a command signal, comprising:

• an input terminal receiving said clock signal, said address signal, said command signal, and an address mode signal designating a timing at which the address signal is entered;
• a mode decode circuit in response to said address mode signal to determine said timing at which the address signal is entered as either one of a first address mode and a second address mode;
• an address latch circuit receiving and latching said address signal from said input terminal at a timing at which said clock signal is activated if said first address mode is designated, and receiving and latching said address signal from said input terminal at the timing at which said clock signal is activated while said command signal is activated if said second address mode is designated;
• a memory cell array having a plurality of normal memory cells arranged in rows and columns;
• a redundant circuit having a plurality of spare memory cell rows and spare memory cell columns for replacing a normal memory cell having a defect;
• a redundancy control circuit receiving said address signal transmitted from said address latch circuit to make a redundancy-based judgement for issuing an instruction to perform a redundancy-based repair operation if said address signal is associated with an address of said normal memory cell having the defect;
• an address decode circuit in response to said address signal transmitted from said address latch circuit to generate an address decode signal for selectively activating one of rows of said normal memory cells and one of columns of said normal memory cells;
• a redundant decode circuit in response to activation of said clock signal to selectively activate one of said spare memory cell rows and said spare memory cell columns if said redundancy-based repair operation is performed;
• and
• a drive circuit in response to activation of said clock signal to selectively activate one of rows and one of columns of said normal memory cells corresponding to said address decode signal.

A semiconductor memory device operating synchronously with a clock signal to read or write a data signal in response to a row address signal and a column address signal, comprising:

• a) a memory cell array having normal memory cells arranged in rows and columns said memory cell array divided into a plurality of memory cell blocks arranged in a first number of rows and a second number of columns:
• b) a redundant circuit having spare memory cell rows and spare memory cell columns for replacing a normal memory cell having a defect, said redundant circuit having a plurality of spare column circuits each provided to each row of said memory cell blocks and each of said spare column circuits having a plurality of spare memory cells arranged in rows and columns;
• c) a third number of global data buses and a plurality of data I/O lines for transmitting said data signal,
• said plurality of data I/O lines having normal data I/O lines equal in number to said third number and provided to each memory cell block group formed of said memory cell blocks equal in number to said first number and adjacent to each other in a column direction each of said normal data I/O lines provided to a fourth number of columns of said normal memory cells, and
• said plurality of data I/O lines further having a plurality of spare column data I/O lines provided commonly to said spare column circuits and provided for columns equal in number to said fourth number of said spare memory cells;
• d) a redundancy control circuit receiving said address signal to make a redundancy-based judgement for issuing an instruction to perform a redundancy-based repair operation if said address signal is associated with an address of said normal memory cell having the defect, and designating a manner in which said data I/O lines are connected in said redundancy-based repair operation, said data line switch signals including shift set signals and redundant column switch signals;
• and
• e) a data line connection circuit provided to each said memory cell block group for connecting said data I/O lines equal in number to said third number selected from said plurality of data I/O lines selectively with said third number of global data buses respectively under control by said redundancy control circuit,
• said data line connection circuit including:
• a normal data line shift circuit in response to said shift set signals to connect (L−M) (M:
• integer of 0 to L) normal data I/O lines except for M normal data I/O lines corresponding to normal memory cells having said defects respectively with first to (L−M) th global data buses, and
• a spare column data line switching circuit in response to said redundant column switch signals to connect (L−M+1) th to L-th global data buses respectively with M of said spare column data I/O lines when M exceeds zero.