US 6,272,055 B1 · Semiconductor memory device

Abstract

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

Claims14

Dependent claims

A semiconductor memory device comprising:

a boosted low level potential applying circuit for applying a boosted low level potential higher than a low level potential of a word line to a boosted low level line;
a word driver including an n channel transistor coupled between the word line and a first node;
a switch circuit including a first transistor coupled between the boosted low level line and the first node, and a second transistor coupled between the first node and a second node to which the low level potential of the word line is applied;
and
a sense amplifier for amplifying a signal on a bit line and for rendering a potential of the bit line the boosted low level potential.

2 more elements

A semiconductor memory device comprising:

a boosted low level potential applying circuit for applying a boosted low level potential higher than a low level potential of word lines to a boosted low level line;
a plurality of word driver groups each including a plurality of word drivers provided corresponding to the word lines respectively, each of the plurality of word drivers including an n channel transistor coupled to a corresponding one of the word lines;
a plurality of switch circuits provided corresponding to said plurality of word driver groups respectively, each including a first transistor coupled between the boosted low level line and sources of the n channel transistors included in a corresponding one of said plurality of word driver groups and each including a second transistor coupled between the sources of the n channel transistors and a second node to which the low level potential of word lines is applied;
and
a sense amplifier for amplifying a signal on a bit line and for rendering a potential of the bit line the boosted low level potential.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/168,962Filed 9 Oct 1998 · continuation

Priority

JP 5-25732814 Oct 1993

Granted

7 Aug 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 5/14
Details of stores covered by group G11C11/00: power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or…
G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 7/062
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of non-latching type, e.g. comparators,…

Family

Application08/312,968Parent of this continuation-in-part · filed 30 Sep 1994

Application08/899,143Parent of this continuation · filed 23 Jul 1997

US 5,943,273 AParent of this continuation

Application08/899,143Parent of this continuation-in-part

US 5,687,123 AParent of this continuation-in-part

US 6,272,055 B1This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims14