Twin-cell memory architecture with shielded bitlines for embedded memory applications

A method of substantially eliminating crosstalk in a twin-cell, folded bitline memory array comprising:

• (a) providing a twin-cell, folded bitline memory array which includes a plurality of bitlines arranged in one direction in parallel with each other with every other bitline constituting a bitline pair;
• a plurality of sense amplifiers being arranged in a line, wherein each sense amplifier is interconnected to two adjacent bitline pairs;
• a plurality of wordlines arranged in a direction intersecting said plurality of bitlines, wherein a single wordline is coupled to every other bitline;
• and isolation means located on said plurality of bitlines, said isolation means being arranged such that when every other bitline of said plurality of bitlines is being sensed, the adjacent bitlines of said plurality of bitlines are held at a predetermined potential by a clamping means;
• and
• (b) switching on every other isolation means so as to activate every other bitline of said array, while holding other bitlines of said bitline pair not sensed at said predetermined voltage level with said clamping means.