Method and apparatus for providing an embedded flash-EEPROM technology
AssigneeVLSI Technology, Inc.
InventorsJames A. Cunningham, Richard A. Blanchard
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Abstract
Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
Claims8
A split-gate flash memory cell comprising:
- a tunnel oxide formed by oxidation of a textured monocrystalline substrate;
- a first floating gate electrode formed over said tunneling oxide;
- a gate oxide, separate from the tunneling oxide, formed on a non-textured portion of said monocrystalline substrate;
- and
- a second control electrode formed over said first floating gate electrode and said gate oxide.
A method for programming a split-gate flash memory cell comprising the steps of:
- increasing a threshold voltage on a first floating gate electrode by channel initiated secondary electrons, said first floating gate electrode being formed over a tunnel oxide that has been oxidized on a textured monocrystalline substrate;
- and
- applying a voltage to a second control electrode formed over said first floating gate electrode and a gate oxide, said gate oxide being separate from the tunneling oxide and being formed on a non-textured portion of said monocrystalline substrate.
Dependencies are inferred from the claim text.