Non-volatile semiconductor memory device having increased operating speed

An electrically erasable and programmable non-volatile semiconductor memory device comprising:

• first, second and third memory cells, each of which has a control gate, a floating gate, a drain and a source, and is set either to an erase state having a low threshold voltage or to a program state where more electrons than in said erase state are stored in the floating gate for attaining a threshold voltage higher than the threshold voltage attained in said erase state;
• a first bit line connected to the drain of said first memory cell;
• a second bit line connected to the drain of said second memory cell;
• a third bit line connected to the drain of said third memory cell;
• means for setting one of said second and third memory cells to said erase state and the other to said program state;
• means for connecting said second bit line to said third bit line in a given read cycle;
• means for setting said first, second and third bit lines to a predetermined precharge potential at an initial stage of said read cycle;
• and
• means for sensing a state of said first memory cell in said read cycle by using a potential of said second and third bit lines, connected to each other, that is lowered from said precharge potential by a drain current drained from said second and third bit lines by at least one of said second and third memory cells.

In a non-volatile semiconductor memory device having:

• first, second and third memory cells, each of which has a control gate, a floating gate, a drain and a source, and is set either to an erase state having a low threshold voltage or to a program state where more electrons than in said erase state are stored in the floating gate for attaining a threshold voltage higher than the threshold voltage attained in said erase state;
• a first bit line connected to the drain of said first memory cell;
• a second bit line connected to the drain of said second memory cell;
• and
• a third bit line connected to the drain of said third memory cell, a circuit for generating a reference potential comprising:
• means for setting one of said second and third memory cells to said erase state and the other to said program state;
• means for connecting said second bit line to said third bit line in a given read cycle;
• and
• means for setting said first, second and third bit lines to a predetermined precharge potential at an initial stage of said read cycle,
• wherein a potential of said second and third bit lines, connected to each other, that is lowered from said precharge potential by a drain current drained from said second and third bit lines by at least one of said second and third memory cells is used as a reference potential for sensing a state of said first memory cell in said read cycle.

A method of generating a reference potential in a non-volatile semiconductor memory device, said non-volatile semiconductor memory device comprising:

• first, second and third memory cells, each of which has a control gate, a floating gate, a drain and a source, and is set either to an erase state having a low threshold voltage or to a program state where more electrons than in said erase state are stored in the floating gate for attaining a threshold voltage higher than the threshold voltage attained in said erase state;
• a first bit line connected to the drain of said first memory cell;
• a second bit line connected to the drain of said second memory cell;
• a third bit line connected to the drain of said third memory cell;
• said method of generating said reference potential comprising the steps of:
• setting one of said second and third memory cells to said erase state and the other to said program state;
• connecting said second bit line to said third bit line in a given read cycle;
• and
• setting said first, second and third bit lines to a predetermined precharge potential at an initial stage of said read cycle,
• wherein a potential of said second and third bit lines, connected to each other, that is lowered from said precharge potential by a drain current drained from said second and third bit lines by at least one of said second and third memory cells is used as a reference potential for sensing a state of said first memory cell in said read cycle.