Apparatus and method for programming voltage protection in a non-volatile memory system

A method of controlling operation of a memory system, comprising:

• providing a voltage divider circuit having first and second voltage dividers arranged in parallel between a programming voltage node and a circuit common;
• applying a programming voltage to the programming voltage node to generate first and second intermediate voltages at respective first and second divider nodes when the programming voltage is at respective first and second voltage levels;
• comparing the first and second intermediate voltages to a reference voltage;
• and
• initiating a programming operation when the programming voltage is in a first voltage range or a second voltage range, the first voltage range having a lower limit defined by the comparison between the first intermediate voltage and the reference voltage, the second voltage range having an upper limit defined by the comparison between the second intermediate voltage and the reference voltage.

A method of controlling operation of a memory system, comprising:

• providing a dual resistance ladder including first and second legs in parallel for allowing current to flow between a programming voltage node and a circuit common;
• applying a programming voltage to the progeamming voltage node to generate first and second intermediate voltages at respective first and second ladder nodes when the programming voltage is at respective first and second voltage levels;
• comparing the first and second intermediate voltages to a reference voltage;
• and
• initiating a programming operation when the programming voltage is in a first or a second acceptable initial voltage range, the first acceptable initial voltage range having a lower limit defined by the comparison between the first intermediate voltage and the reference voltage, the second acceptable initial voltage range having an upper limit defined by the comparison between the intermediate and the reference voltages.

A method of controlling operation of a memory system, comprising:

• providing a dual resistance ladder including first and second legs in parallel for allowing current to flow between a programming voltage node and a circuit common;
• applying a programming voltage to the programming voltage node to generate first and second intermediate voltages at respective first and second ladder nodes when the programming voltage is at respective first and second voltage levels;
• comparing the first and second intermediate voltages to a reference voltage;
• initiating a programming operation when the programming voltage is in a first or a second acceptable initial voltage range, the first acceptable initial voltage range having a lower limit defined by the comparison between the first intermediate voltage and the reference voltage, the second acceptable initial voltage range having an upper limit defined by the comparison between the second intermediate and reference voltages;
• and
• continuing the initiated programming operation when the programming voltage stays within a first or a second acceptable execution voltage range, the first acceptable execution voltage range having a lower limit less than the lower limit of the first acceptable initial voltage range, the second acceptable execution voltage range having a lower limit less than a lower limit of the second acceptable initial voltage range.