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US 6,272,047 B1Granted
Flash memory cell
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Paul J. Rudeck, Chun Chen
Life of this patent
Estimating the term…
Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
Claims22
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a common substrate, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a semiconductor substrate, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region, a source region comprising an arsenic doped region abutting a heavily doped boron region, and a channel region formed in a common substrate, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region comprising an arsenic doped region abutting a phosphorous doped region, a source region, and a channel region formed in a common substrate, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a common substrate, the channel region comprising a first boron region and a second boron region, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a common substrate, the channel region comprising a first boron region and a second boron region in which the first boron region is more lightly doped than the second boron region and the first boron region forms a junction with the drain region, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
A flash memory cell comprising:
- a control gate, a drain region, a source region, and a channel region formed in a common substrate, the channel region comprising a first boron region and a second boron region in which the first boron region is more lightly doped than the second boron region and the second boron region is located below the first boron region and extends toward the drain region without joining the drain region, the flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and about six volts across a shallow deep-depletion region created near the drain region as a result of a first voltage applied to the control gate, a second voltage applied to the drain region, and a third voltage applied to the source region.
Dependencies are inferred from the claim text.