Individual source line to decrease column leakage
AssigneeAdvanced Micro Devices, Inc.
InventorHisayuki Shimada
Life of this patent
Estimating the term…
Abstract
A flash memory device and a method to read the flash memory device to decrease leakage current during read. The flash memory device has a source line control circuit connected to the sources of memory cells in a row and during read the source line control circuit connects the sources of the memory cells in a row to ground.
Claims5
A method of reading a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device composed of multiple memory cells each having a source, drain, control gate, wherein the memory cells are organized in rows and columns with each memory cell in a row connected to a wordline, each memory cell in a column connected to a bitline and each source of a memory cell in a row connected to a source line;
- the method comprising:
- (a) applying a voltage of approximately 4-5 volts to the wordline attached to the control gate of a cell selected to be read;
- (b) applying a voltage of approximately 1 volt to the bitline attached to the drain of the cell selected to be read;
- (c) attaching the source line attached to the source of the cell selected to be read to ground;
- (d) opening wordlines attached to control gates of cells not selected to be read;
- (e) opening bitlines attached to drains of cells not selected to be read;
- and
- (f) opening sourceline attached to sources of cells not selected to be read.
A method of reading a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) device composed of multiple memory cells each having a source, drain, control gate, wherein the memory cells are organized in rows and columns with each memory cell in a row connected to a wordline, each memory cell in a column connected to a bitline and each source of a memory cell in a row connected to a source line;
- the method comprising:
- (a) applying a voltage of approximately 4-5 volts to the wordline attached to the control gate of a cell selected to be read;
- (b) applying a voltage of approximately 1 volt to the bitline attached to the drain of the cell selected to be read;
- (c) attaching the source line attached to the source of the cell selected to be read to ground;
- (d) opening wordlines attached to control gates of cells not selected to be read;
- (e) applying a voltage to bitlines attached to drains of cells not selected to be read and applying a voltage to sourcelines attached to sources of cells not selected to be read such that a drain to source voltage VDS is substantially equal to zero.
Dependencies are inferred from the claim text.