Semiconductor storage device and method of driving thereof
AssigneeRohm Co., Ltd.
InventorsHiroki Yamamoto, Yoshihiro Tada
Life of this patent
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Abstract
In a semiconductor storage device comprising a plurality of memory cells P formed in a matrix form in a semiconductor substrate, write and read for each of which is carried out through a word line and bit line, wherein each said memory cells includes a first and a second memory transistor MT1 and MT2 connected in series. In this configuration, the semiconductor storage device with high reliability which produces abnormality in operation can be provided.
Claims9
A semiconductor storage device comprising a plurality of memory cells each having a select transistor and a memory transistor means, for each of which write and read is carried out in such a manner that a voltage is applied to a word line and bit line of the memory transistor means so that write and erasure of data is executed by tunneling of electrons through a gate insulating film, wherein said memory transistor means comprises two memory transistors connected in series, one said memory transistor being a main memory transistor and the other said memory transistor being an auxiliary memory transistor, so that only during the period when said main memory transistor is broken, the semiconductor storage device is driven by said auxiliary memory transistor.
A method for driving a semiconductor storage device wherein a memory cell comprises a series connection of a select transistor and source and drain regions of a first and a second memory transistor for which write and erasure of data are executed through tunneling of electrons through a gate insulating film, said first memory transistor being a main memory transistor and said second memory transistor being an auxiliary memory transistor, comprising the steps of:
- applying a high potential to control gates of said first and said second memory transistors, respectively, to set said bit line and said source line at a low potential so that each memory cell at issue is placed in an erased state;
- applying the high potential to said bit line to set the control gates of said first and said second memory transistors at the low potential so that data is written in said first memory transistor;
- setting said bit line and the control gate of said first memory transistor at the high potential and setting the control gate of said second memory transistor at the low potential so that data is written in said second memory transistor;
- and
- applying a reference potential to the control gates of said first and said second memory transistor to produce an applied voltage to said bit line so that the data is read from the memory cell at issue,
- wherein only during the period when said main memory transistor is broken, the semiconductor storage device is driven by said auxiliary memory transistor.
Dependencies are inferred from the claim text.