MTJ MRAM parallel-parallel architecture

Magnetic tunnel junction random access memory architecture comprising:

• an array of memory cells arranged in rows and columns, each memory cell including a magnetic tunnel junction and a control transistor connected in series;
• and
• the array of memory cells including a plurality of columns with each column including a global bit line coupled to a control circuit, each column further including a plurality of local bit lines coupled in parallel to the global bit line and a plurality of groups of memory cells with each group including a plurality of memory cells connected in parallel between the local bit line and a reference potential;
• one of the columns of memory cells, including a global bit line and local bit lines, connected to provide a reference signal output;
• and
• an output circuit including a first and a second comparator circuit each having a first input terminal connected to receive the reference signal output and a second input terminal connected to receive a data output signal from at least one global bit line on each opposite side of the reference column, respectively, the first comparator circuit comparing the data output signal from a global bit line on one side of the reference column to the reference signal output and the second comparator circuit comparing the data output signal from a global bit line on an opposite side of the reference column to the reference signal output.

Magnetic tunnel junction random access memory architecture comprising:

• an array of memory cells arranged in rows and columns, each memory cell including a magnetic tunnel junction and a control transistor connected in series;
• and
• the array of memory cells including a plurality of columns with each column including a global bit line coupled to a control circuit, each column further including a plurality of local bit lines coupled in parallel to the global bit line and a plurality of groups of memory cells with each group including a plurality of memory cells connected in parallel between the local bit line and a reference potential, and each local bit line including a control transistor;
• the control transistors in the local bit lines being arranged in rows and each control transistor including a control terminal, each row of control transistors having a select line attached to the control terminal of each control transistor in the row and to a control circuit for selecting a local bit line of each global bit line;
• and
• an output circuit including column select circuitry and a differential comparator circuit having a first input terminal connected through the column select circuitry to receive a first data output signal from a first global bit line and a second input terminal connected through the column select circuitry to receive a second data output signal from a second global bit line, the comparator circuit differentially comparing the first and second data output signals.