Temperature insensitive capacitor load memory cell
AssigneeAgere Systems Guardian Corp.
InventorsJames T. Clemens, Philip W. Diodato, Yiu-Huen Wong
Life of this patent
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Abstract
An apparatus and method for constructing a temperature insensitive memory cell. This temperature insensitive memory cell operates as a static random access memory (SRAM) cell if a particular capacitor and transistor configuration is used. The temperature insensitive memory cell apparatus includes at least one transistor having a current leakage, and at least one capacitor electrically connected to the transistor. The capacitor acts as a load element for the memory cell. The capacitor has a temperature dependent capacitor leakage that tracks the current leakage of transistor as said at least one transistor as the transistor varies with temperature.
Claims17
A temperature insensitive memory cell apparatus comprising:
- at least one transistor having a current leakage;
- and
- at least one capacitor electrically connected to said transistor to act as a load element for said memory cell, said at least one capacitor having a temperature dependent capacitor leakage that tracks said current leakage as said at least one transistor varies with temperature.
A temperature insensitive memory cell apparatus comprising:
- first and second bit lines;
- a first transistor, said first transistor connected to said first bit line on a first transistor first contact;
- a second transistor, said second transistor electrically connected to said second bit line on a second transistor first contact;
- a first capacitor, said first capacitor electrically connected to a source current on a first capacitor first contact;
- a second capacitor, said second capacitor electrically connected to said source current on a second capacitor first contact;
- a third transistor, said third transistor electrically connected to a ground contact on a third transistor first contact, a second contact of said third transistor being electrically connected to a second contact of said first capacitor;
- a fourth transistor, said fourth transistor electrically connected to a ground contact on a fourth transistor first contact, a second contact of said fourth transistor being electrically connected to a second contact of said second capacitor;
- wherein a second contact of said first transistor is electrically connected to said fourth transistor second contact and a third transistor third contact, and
- wherein a first capacitor and said second capacitor act as a load element for said memory cell, said first capacitor and said second capacitor having a temperature dependent capacitor leakage that tracks a current leakage of said temperature insensitive memory cell as said temperature insensitive memory cell varies with temperature.
A method for forming a temperature insensitive memory cell apparatus, comprising the steps of:
- providing a substrate;
- forming a source contact on said substrate, wherein said source contact comprises a field oxide dielectric layer;
- forming a drain contact on said substrate, wherein said drain contact comprises a field oxide dielectric layer;
- forming a gate electrode on top of said field oxide to form a transistor;
- forming a first contact on said source contact;
- forming a first metal layer bit line on said first contact to connect said first contact to said first metal layer bit line;
- forming a second contact on said drain contact;
- fabricating a first plug on said second contact;
- forming a capacitor on said first plug, said capacitor including a dielectric having a temperature dependent capacitor leakage that tracks a current leakage of said transistor as said transistor varies with temperature;
- forming a second metal layer on said capacitor;
- fabricating a second plug on said second metal layer;
- and
- forming a third metal layer on said second plug.
Dependencies are inferred from the claim text.