Ferroelectric memory device and method for generating reference level signal therefor

Abstract

A ferroelectric memory device of the present invention includes at least one memory cell which includes a semiconductor transistor and a ferroelectric capacitor, the ferroelectric memory device reading out data from each of the at least one memory cell and comparing the read data with a reference level signal to amplify a signal corresponding to the data read out from the at least one memory cell. The ferroelectric memory device further includes: at least one of an external voltage detection circuit for detecting a level of a voltage externally provided to the ferroelectric memory device and a temperature detection circuit for detecting an ambient temperature around the ferroelectric memory device; a reference signal generation circuit connected to the at least one of the external voltage detection circuit and the temperature detection circuit for outputting a potential based on an output from the at least one of the external voltage detection circuit and the temperature detection circuit; and a reference level adjustment section for adjusting the potential output from the reference signal generation circuit into a suitable reference level signal.

Dependencies are inferred from the claim text.