Status bits for cache memory

Abstract

Data processing apparatuses provided comprising a memory operable to store a plurality of data words, each data word being associated with at least one status bit giving information regarding a status of said data word; a status bit store operable to store said status bits within a hierarchical relationship such that a combined status relating to a plurality of first level status bits at a first level within said hierarchical relationship is indicated by a second level status bit at a second level within said hierarchical relationship, said second level being higher in said hierarchical relationship than said first level; and status querying logic operative to determine a status of a data word within said memory by examining status bits within said status bit store starting at a top level within said hierarchical relationship and working down through said hierarchical relationship until a status bit is reached that indicates said status of said data word independently of any status bits lower in said hierarchical relationship. In this way a global or large-scale change to status bits may be made by modifying relatively few higher level status bits within the hierarchical relationship thereby achieving a high speed change with reduced levels of special purpose hardware being required.

Dependencies are inferred from the claim text.