Dual port memory system for buffering asynchronous input to a raster scanned display

A method for controlling the reading from and writing to dual-port memory used as a buffer for storing digital video data to be displayed on a raster scanned display, the video data being written to a write address in said memory and being read from a read address in said memory, wherein the video data is received asynchronously with respect to the display rate of the raster scanned display, the method comprising the steps of:

• (a) partitioning said memory into an extended buffer including a single frame buffer capable of storing one frame of the video data, and an extension buffer for storing additional said video data, wherein said extension buffer is a contiguous extension of said single frame buffer;
• (b) receiving a write frame sync signal;
• (c) determining a number of lines of separation in said memory between a present said read address and a present said write address;
• (d) in response to a situation wherein said separation is not more than a predetermined number of said lines:
• if buffer wrap-around mode is set,
• writing the video data to said extended buffer;
• and
• reading the video data from said extended buffer;
• if said buffer wrap-around mode is not set,
• setting said buffer wrap-around mode;
• continuing to read the video data from said single frame buffer;
• and
• writing the video data to said extended buffer space;
• (e) in response to a situation wherein said separation is more than said predetermined number of lines:
• if said buffer wrap-around mode is set,
• terminating said buffer wrap-around mode;
• and
• processing the video data by writing to and reading from said extended buffer;
• if said buffer wrap-around mode is not set,
• processing the video data by writing to and reading from said single frame buffer.

A system for managing video data to be displayed on a raster scanned video display device having dual-port memory connected thereto, wherein said data is written to a write address in said memory, and is read to said display device from a read address in said memory, wherein said memory includes a frame buffer for storing one frame of the video data, and an extension buffer, contiguous to said frame buffer, for storing additional said video data, the system comprising:

• address compare logic for generating a minimum spacing signal when said write address is separated from said read address by a minimum spacing;
• wrap counter logic for generating a wrap mode inhibit signal in response to simultaneously receiving said minimum spacing signal and a write sync signal, and for suppressing said wrap mode inhibit signal in absence of said minimum spacing signal, wherein said wrap mode inhibit signal is suppressed until a predetermined number of said write sync signals have been received;
• gate logic for generating a counter reset signal in response to simultaneously receiving said minimum spacing signal, said wrap mode inhibit signal and said write sync signal;
• a write address counter for incrementing said write address and for initializing said write address in response to said counter reset signal;
• field delay logic for initializing said read address in response to simultaneously receiving said counter reset signal and a read sync signal, if said counter reset signal was received subsequent to the previous said write sync signal;
• and
• a read address counter for incrementing said read address, and for initializing said read address in response to a signal from said field delay logic.

A system for managing video data to be displayed on a raster scanned video display device having dual-port memory connected thereto, wherein said data is written to a write address in said memory, and is read to said display device from a read address in said memory, wherein said memory includes a frame buffer for storing one frame of the video data, and an extension buffer, contiguous to said frame buffer, for storing additional said video data, the system comprising:

• address compare means for generating a minimum spacing signal when said write address is separated from said read address by a minimum spacing;
• wrap counter means for generating a wrap mode inhibit signal in response to simultaneously receiving said minimum spacing signal and a write sync signal, and for suppressing said wrap mode inhibit signal in absence of said minimum spacing signal, wherein said wrap mode inhibit signal is suppressed until a predetermined number of said write sync signals have been received;
• gate means for generating a counter reset signal in response to simultaneously receiving said minimum spacing signal, said wrap mode inhibit signal and said write sync signal;
• a write address counter for incrementing said write address and for initializing said write address in response to said counter reset signal;
• field delay means for initializing said read address in response to simultaneously receiving said counter reset signal and a read sync signal, if said counter reset signal was received subsequent to the previous said write sync signal;
• and
• a read address counter for incrementing said read address, and for initializing said read address in response to a signal from said field delay means.