Flat panel display apparatus and method for interfacing data thereof

A flat panel display apparatus having a flat display panel wherein a resolution thereof is 3S×H (where S and H respectively represent a number of samples of respective red, green and blue per line and a number of horizontal scanning lines) and wherein 3S units of red, green and blue strip-shaped address electrodes are alternately arranged to be driven by upper and lower portions of said panel, said apparatus comprising:

• a memory for entering N subfield data having L (where L≦3N×M;
• N is a bit number of one word of respective red, green and blue, and M is a least integer which is greater than a quotient of S/N) units of one-bit pixel data every one line and having H/2 scanning lines in an interlaced scanning system in a first frame memory area, for, simultaneously, repeating, every data corresponding to one line in a sequential scanning system over G times, reading 3N-bit red, green and blue data in {A+G(n−1)}-numbered sequence (where A is an initial address value of respective data groups, G is a least integer which is greater than a quotient of S/Q and represents a group number, and 1≦n≦Q) among M units of 3N-bit red, green and blue data sequences over Q times in sequence every data corresponding to one line from a second memory area having previous N subfield data stored therein;
• a data interfacing means, including a pair of data storage sections each for provisionally storing data corresponding to upper and lower driving electrodes, for sequentially storing the read 3N/2-bit red, green and blue data over Q times in a first storage area and, for, simultaneously, outputting {(N/2)·Q}-bit data over three times from a second storage area having previous data stored therein, for alternately repeating both reading the data from said first storage area and outputting the data from said second storage area over G times;
• and
• means for sequentially inputting {(N/2)·Q}-bit data from said data interfacing means in parallel over 3G times, and for, in order to drive L/2 address electrodes with the inputted pixel data, driving upper and lower address electrodes, respectively including Q (where Q is a least integer which is greater than a quotient of L/2P) address electrodes driving integrated circuits having both N/2 input pins and P (where P is a common multiple of 3 and N/2) output pins.

A method for interfacing pixel data from a frame memory whose every line has L (where L≦3N×M;

• N is a bit number of one word of respective red, green, and blue, M is a minimum integer which is greater than a quotient of S/N, and S is a number of samples of respective red, green and blue per line) units of one-bit pixel data stored therein to Q (where Q is a least integer which is greater than a quotient of L/2P) units of address electrode driving integrated circuits respectively having both N/2 input pins and P (where P is a common multiple of 3 and N/2) output pins, said method comprising the steps of:
• repeating, every data corresponding to 1 line over G times, reading 3N/2-bit red, green and blue data in {A+G(n−1)}-numbered sequence (where A is an initial address value of respective data groups, G is a least integer which is greater than a quotient of S/(Q/2) and represents a group number, and 1≦n≦Q/2) among M units of 3N/2-bit red, green and blue data sequences over Q/2 times in sequence every data corresponding to 1 lines from said frame memory;
• storing the read 3N/2-bit red, green and blue data over Q/2 times in a first and a second storage areas and, simultaneously, outputting {(N/2)·(Q/2)}-bit data sequences over 6 times from a third and a fourth storage areas having previous data stored therein;
• and
• repeating both reading the data from said first and said second storage areas and outputting the data from said third and said fourth storage areas alternately over G/2 times.

A flat panel display apparatus having a flat display panel wherein a resolution thereof is 3S×H (where S and H respectively represent a number of samples of respective red, green and blue per line and a number of horizontal scanning lines) and wherein 3S units of red, green and blue strip-shaped address electrodes are alternately arranged to be driven by upper and lower portions of said panel, said apparatus comprising:

• a memory for entering N subfield data having L (where L≦3N×M;
• N is a bit number of one word of respective red, green and blue, and M is a least integer which is greater than a quotient of S/N) units of one-bit pixel data every line and having H/2 scanning lines in an interlaced scanning system in a first frame memory area, for, simultaneously, repeating, every data corresponding to one line in a sequential scanning system over G times, reading 3N-bit red, green and blue data in {A+G(n−1)}-numbered sequence (where A is an initial address value of respective data groups, G is a least integer which is greater than a quotient of S/Q and represents a group number, and 1≦n≦Q/2) among M units of 3N-bit red, green and blue data sequences over Q times in sequence every data corresponding to one line from a second memory area having previous N subfield data stored therein;
• a data interfacing means, including a pair of data storage sections each for provisionally storing data corresponding to upper and lower driving electrodes, for sequentially storing the read 3N/2-bit red, green and blue data over Q/2 times in a first and a second storage area, for, simultaneously, outputting {(N/2)·(Q/2)}-bit data over 6 times from a third and a fourth storage areas having previous data stored therein, and for alternately repeating both reading the data from said first and said second storage areas and outputting the data from said third and said fourth storage areas over G/2 times;
• and
• means for, sequentially and alternately, inputting {(N/2)·(Q/2)}-bit data from said data interfacing means in parallel over 3×(G/2) times into integrated circuits of an odd-numbered sequence and of an even-numbered sequence, and for, in order to drive L/2 address electrodes with the inputted pixel data, driving upper and lower address electrodes, respectively including Q (where Q is a least integer which is greater than a quotient of L/2P) address electrodes driving integrated circuits having both N/2 input pins and P (where P is a common multiple of 3 and N/2) output pins.

A method for interfacing pixel data from a frame memory whose every line has L (where L≦3N×M;

• N is a bit number of one word of respective red, green, and blue, M is a minimum integer which is greater than a quotient of S/N, and S is a number of samples of respective red, green and blue per line) units of one-bit pixel data stored therein to Q (where Q is a least integer which is greater than a quotient of L/2P) units of address electrode driving integrated circuits respectively having both N/2 input pins and P (where P is a common multiple of 3 and N/2) output pins, said method comprising the steps of:
• repeating, every data corresponding to 1 line over G times, reading 3N/2-bit red, green and blue data in {A+G(n−1)}-numbered sequence (where A is an initial address value of respective data groups, G is a least integer which is greater than a quotient of M/Q and represents a group number, and 1≦n≦Q/2) among M units of 3N/2-bit red, green and blue data sequences over Q/2 times in sequence every data corresponding to 1 line from said frame memory;
• storing the read 3N/2-bit red, green and blue data over Q/2 times in a first storage area and, simultaneously, outputting {(N/2)·(Q/2)}-bit data sequences over 3 times from a second storage area having previous data stored therein;
• and
• repeating both reading the data from said first storage area and outputting the data from said second storage area alternately over G times.

A flat panel display apparatus having a flat display panel wherein a resolution thereof is 3S×H (where S and H respectively represent a number of samples of respective red, green and blue per line and a number of horizontal scanning lines) and wherein 3S units of red, green and blue strip-shaped address electrodes are alternately arranged to be driven by upper and lower portions of said panel, said apparatus comprising:

• a memory for entering N subfield data having L (where L≦3N×M;
• N is a bit number of one word of respective red, green and blue, and M is a least integer which is greater than a quotient of S/N) units of one-bit pixel data every one line and having H/2 scanning lines in an interlaced scanning system in a first frame memory area, and for, simultaneously, repeating, every data corresponding to one line in a sequential scanning system over G times, reading 3N-bit red, green and blue data in {A+G(n−1)}-numbered sequence (where A is an initial address value of respective data groups, G is a least integer which is greater than a quotient of S/Q and represents a group number, and 1≦n≦Q/2) among M units of 3N-bit red, green and blue data sequences over Q times in sequence every data corresponding to one line from a second memory area having previous N subfield data stored therein;
• a data interfacing means, including a pair of data storage sections each for provisionally storing data corresponding to upper and lower driving electrodes, for sequentially storing the read 3N/2-bit red, green and blue data over Q/2 times in a first storage area, for, simultaneously, outputting {(N/2)·(Q/2)}-bit data over 3 times from a second storage area having previous data stored therein, and for alternately repeating both reading the data from said first storage area and outputting the data from said second storage area over G times;
• and
• means for, sequentially and alternately, inputting {(N/2)·(Q/2)}-bit data from said data interfacing means by serial 3 times in parallel over G times into integrated circuits of an odd-numbered sequence and of even-numbered sequence, and for, in order to drive L/2 address electrodes with the inputted pixel data, driving upper and lower address electrodes, respectively including Q (where Q is a least integer which is greater than a quotient of L/2P) address electrodes driving integrated circuits having both N/2 input pins and P (where P is a common multiple of 3 and N/2) output pins.