Data transmission system employing clock-enriched data coding and sub-harmonic de-multiplexing

Apparatus for converting a serial data stream to a plurality of data streams, the apparatus comprising:

• a filter circuit to extract timing information, previously added to the serial data stream, from the serial data stream;
• a clock generation circuit, operatively coupled to the filter circuit, to generate a plurality of clock signals from the extracted timing information, wherein the plurality of clock signals has a common frequency which is less than a frequency associated with the serial data stream;
• and
• a plurality of de-multiplexer circuits, operatively coupled to the clock generation circuit, to convert the serial data stream to a plurality of parallel data streams respectively using the plurality of clock signals.

Apparatus for converting a serial data stream to a plurality of data streams, the apparatus comprising:

• a filter circuit to extract timing information, previously added to the serial data stream, from the serial data stream;
• a clock generation circuit, operatively coupled to the filter circuit, to generate at least one clock signal from the extracted timing information wherein the at least one clock signal has a frequency which is not equivalent to a frequency associated with the serial data stream;
• and
• a plurality of de-multiplexer circuits, operatively coupled to the clock generation circuit, to convert the serial data stream to a plurality of parallel data streams using the at least one clock signal.

A data transmission system, comprising:

• a data transmitter operable to enrich a serial data stream with timing information;
• and
• a data receiver, operatively coupled to the data transmitter, operable to:
• (i) recover the timing information from the serial data stream to generate a plurality of clock signals, each clock signal having a common frequency and a different phase associated therewith, the common frequency being less than a frequency associated with the serial data stream, and (ii) convert the serial data stream to a plurality of parallel data streams respectively using the plurality of clock signals.