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US 6,271,773 B1Granted
Coherent sampling method and apparatus
AssigneeTeratec Corporation
InventorKensuke Kobayashi
Life of this patent
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Abstract
A coherent sampling method and apparatus in which synchronizing signal is synchronously obtained from an input signal. The synchronizing signal repetition time period is measured and thereby the clock cycle time, which executes a coherent sampling for the input signal, is sought. A clock generator generates the clock sought and because the sampling clock being optimized for the input signal is used, no waveform missing phenomena happens and a reproduced waveform is immediately displayable.
Claims10
A coherent sampling method comprising the steps of;
- digitizing (10) an input signal (1) sampled by a clock (3) to obtain a digital data (20);
- acquisition storing (30) for storing the digital data (20);
- synchronizing (100) with a trigger pulse as a reference trigger (RT1), which is applied after a first hold timing (h0) showing an end of a hold time duration (Tmh), among trigger pulses of a trigger (2) synchronizing the input signal (1) to recurrently obtain pulses as a synchronizing signal (52);
- operating a timebase (200) recurrently
- for measuring a first time difference (Ts1) between a first pulse of the synchronizing signal (52) synchronizing with the first reference trigger (RT1) and a clock of timing (c1) of the clock (3) applied thereafter,
- for providing a second hold timing (h1), which shows an end of the hold time duration (Tmh), delayed by a delay time Td (=(Tc−Ts1) from a clock timing (c11) of the clock (3) applied just before the end of the hold time duration (Tmh), in which the delay time Td is a time difference between a clock cycle time (Tc) of the clock (3) and the first time difference (Ts1),
- for receiving a second pulse of the synchronizing signal (52) synchronizing with a second reference trigger (RT2) of the trigger (2), and
- for measuring a second time difference (Ts2) between the second pulse of the synchronizing signal (52) and a clock of timing (c13) of the clock (3) applied thereafter;
- processing (40) recurrently,
- for determining a number of time bins M(=Tc/Tres) by dividing the clock cycle time (Tc) by a predetermined time resolution (Tres),
- for getting a time difference variation δTs(=Ts2−Ts1) between the first time difference (Ts1) and the second time difference (Ts2),
- for obtaining a reference trigger time period (Trr) between the first reference trigger (RT1) and the second reference trigger (RT2),
- for seeking coherent sampling conditions, by finding an integer Y that is a number (Floor[Trr/Tcr]) of pulses of the reference clock (RC) with a clock cycle time Trc for the reference trigger time period Trr, and by finding an integer X (Ceiling or Floor[Mod[Trr,Tcr](M/Tcr)]) that is prime to and is less than the number of time bins M,
- for calculating a new clock cycle time (Tc1) given by an equation of Tc,
- Tc=Trr/(Y+(X/M))
- for deciding a time position of the stored digital data (20) to be displayed on a basis of the first and second reference triggers (RT1 and 2) and of each of time points (SP) sampled by the clock (3), and
- for instructing (48) to store waveform data to be displayed;
- generating (300) recurrently the clock (3) of the new clock cycle time (Tc1) so as to satisfy the coherent sampling conditions;
- and
- storing (50) the waveform data to be displayed by the instruction (48) of the processing (40) step.
17 more elements
A coherent sampling apparatus comprising;
- digitizing means (10) for digitizing an input signal (1) sampled by a clock (3) to obtain a digital data (20);
- acquisition storing means (30) for storing the digital data (20);
- synchronizing means (100) for synchronizing with a trigger pulse as a reference trigger (RT1), which is applied after a first hold timing (h0) showing an end of a hold time duration (Tmh), among trigger pulses of a trigger (2) synchronizing the input signal (1) to recurrently obtain pulses as a synchronizing signal (52);
- timebase means (200)
- for recurrently measuring a first time difference (Ts1) between a first pulse of the synchronizing signal (52) synchronizing with the first reference trigger (RT1) and a clock of timing (c1) of the clock (3) applied thereafter,
- for recurrently providing a second hold timing (h1), which shows an end of the hold time duration (Tmh), delayed by a delay time Td (32 Tc−Ts1) from a clock timing (c11) of the clock (3) applied just before the end of the hold time duration (Tmh), in which the delay time Td is a time difference between a clock cycle time (Tc) of the clock (3) and the first time difference (Ts1),
- for recurrently receiving a second pulse of the synchronizing signal (52) synchronizing with a second reference trigger (RT2) of the trigger (2), and
- for recurrently measuring a second time difference (Ts2) between the second pulse of the synchronizing signal (52) and a clock of timing (c13) of the clock (3) applied thereafter;
- processing means (40)
- for recurrently determining a number of time bins M(=Tc/Tres) by dividing the clock cycle time (Tc) by a predetermined time resolution (Tres),
- for recurrently getting a time difference variation δTs(=Ts2−Ts1) between the first time difference (Ts1) and the second time difference (Ts2),
- for recurrently obtaining a reference trigger time period (Trr) between the first reference trigger (RT1) and the second reference trigger (RT2),
- for recurrently seeking coherent sampling conditions, by finding an integer Y that is a number (Floor[Trr/Tcr]) of pulses of the reference clock (RC) with a clock cycle time Tcr for the reference trigger time period Trr, and by finding an integer X (Ceiling or Floor[Mod[Trr,Tcr](M/Tcr)]) that is prime to and is less than the number of time bins M,
- for recurrently calculating a new clock cycle time (Tc1) given by an equation of Tc,
- Tc=Trr/(Y+(X/M))
- for recurrently deciding a time position of the stored digital data (20) to be displayed on a basis of the first and second reference triggers (RT1 and 2) and of each of time points (SP) sampled by the clock (3), and
- for recurrently instructing (48) to store waveform data to be displayed;
- generating means (300) for generating recurrently the clock (3) of the new clock cycle time (Tc1) so as to satisfy the coherent sampling conditions;
- and
- storing means (50) for recurrently storing the waveform data to be displayed by the instruction (48) of the processing means (40).
17 more elements
Dependencies are inferred from the claim text.