Back to results
US 6,271,729 B1Granted
Phase-locked loop or delay-locked loop circuitry for programmable logic devices
AssigneeAltera Corporation
InventorsChiakang Sung, Joseph Huang, Bonnie I. Wang, Robert R. N. Bielby
Life of this patent
Estimating the term…
Abstract
A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
Claims13
A programmable logic device comprising:
- PLL/DLL circuitry configured to receive an input clock signal and to produce modified and pilot clock signals which are variably shifted in phase relative to the input clock signal;
- a clock signal distribution network configured to distribute the modified clock signal to circuitry on the programmable logic device that makes use of the modified clock signal;
- and
- feedback loop circuitry configured to substantially parallel and duplicate a portion of the clock signal distribution network and to convey the pilot signal back to the PLL/DLL circuitry for use in determining a phase shift of the modified clock signal relative to the input clock signal.
1 more element
Dependencies are inferred from the claim text.