Gate circuit
AssigneeKabushiki Kaisha Toshiba
InventorsKimihiro Hoshi, Takeo Kanai
Life of this patent
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Abstract
In a gate circuit having a turn-off gate circuit composed of: OFF gate power source Eoff of which one terminal is connected to the emitter of semiconductor switching element 81, and switch SWoff that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1 via resistor Rg, the gate circuit is provided with second switch SWoff2 that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1. By closing second switch SWoff2 at the timing at which the turn-off operation is completed, it will connect to OFF gate power source Eoff without passing through a resistor.
Claims8
A gate circuit having a turn-off gate circuit which comprising:
- a first OFF gate power source of which one terminal that becomes the power source when a semiconductor switching element turns off is connected to an emitter of the semiconductor switching element;
- a first switch that connects the other terminal of said first OFF gate power source and a gate of said semiconductor switching element via a first resistor;
- a second OFF gate power source, of which one terminal that has a greater absolute value than said first OFF gate power source is connected to an emitter of said semiconductor switching element;
- and
- a second switch for connecting the other terminal of said second OFF gate power source and said gate of said semiconductor switching element,
- wherein said second switch is connected to said gate of said semiconductor switching element via a second resistor that has a smaller resistance than said first resistor, and said second switch is closed at a specified time interval after said first switch has been closed.
A gate circuit according to claim 2, wherein:
- said second switch is closed if the gate voltage falls to a specified voltage or below.
A gate circuit that connects in parallel principal circuit emitter terminals of a plurality of semiconductor switching elements, and is also connected to a negative bias source of said gate circuit by said emitter terminals for plural gates of said plural semiconductor switching elements being connected in parallel, comprising:
- resistors respectively for connecting said emitter terminals for said plural gates and said negative bias of said gate circuit;
- and switches for shorting out said resistors.
Dependencies are inferred from the claim text.