Level shifter

A level shifter comprising:

• an input terminal for receiving an input signal having low and high voltage states;
• an output terminal for providing an output signal having low and high voltage states, wherein a voltage of the high voltage state of the output signal is higher than a voltage of the high voltage state of the input signal;
• an input stage coupled to the input terminal and comprising:
• a first inversion circuit that receives the input signal and generates a first internal control signal that represents an inversion of the input signal;
• and
• a second inversion circuit coupled to the first inversion circuit that receives the first internal control signal and generates a second internal control signal that represents an inversion of the first internal control signal;
• wherein both the first and second inversion circuits are powered by a low power supply voltage that generates a voltage approximately equivalent to the voltage of the high voltage state of the input signal such that voltages of the first and second internal control signals are approximately equivalent to the voltage of the high voltage state of the input signal;
• a low state voltage translation circuit generating a bias signal when the input signal is in its low voltage state, the low state voltage translation circuit coupled to the input stage and receiving the first internal control signal and comprising:
• a plurality of low state PMOS transistors coupled to the low power supply voltage and arranged as a current mirror with two current paths such that current flowing through each of the two current paths is substantially equivalent to each other, wherein current flows through the current mirror when the first internal control signal is high;
• and
• a first bipolar device having its collector terminal and its base terminal coupled to a drain terminal of one of the plurality of low state PMOS transistors of the current mirror, its emitter terminal coupled to a low voltage potential, and its base terminal providing the bias signal, such that when current is flowing through the current mirror the bias signal is high;
• a high state voltage translation circuit adapted to couple a high power supply voltage to the low voltage potential and to generate a bias voltage at a high state output node, wherein the high power supply voltage is approximately equivalent to the voltage of the high voltage state of the output signal, the high state voltage translation circuit comprising:
• a plurality of high state PMOS transistors coupled to the high power supply voltage and arranged as a voltage reducing circuit with a voltage drop across each of the plurality of high state PMOS transistor approximately equal to each other and whereby each of the plurality of high state PMOS transistors reduces a voltage of the high power supply voltage;
• a plurality of voltage reducing NMOS transistors arranged to receive the first internal control signal and generate a reduced voltage signal when the first internal control signal is high;
• and
• first and second NMOS transistors controlling a flow of current through the voltage reducing circuit, the first and second NMOS transistors having their drain terminals coupled to a drain of one of the plurality of high state PMOS transistors and their source terminals coupled to the low voltage potential, the first NMOS transistor having its gate coupled to the second internal control signal such that the first NMOS transistor turns on when the input signal is high, the second NMOS transistor having its gate coupled to the reduced voltage signal generated by the plurality of voltage reducing NMOS transistors such that the second NMOS transistor turns on when the input signal is low;
• and
• an output stage providing the output signal comprising:
• a PMOS pull-up transistor connected to the high power supply voltage and controlled by the bias voltage generated by the high state voltage translation circuit to couple the high power supply voltage to the output terminal when the input signal is high to pull the output signal to its high voltage state, wherein a current flowing through the PMOS pull-up transistor approximately mirrors a current flowing through the voltage reducing circuit of the high state voltage translation circuit;
• and
• a second bipolar device adapted to pull the output signal to its low voltage state when the input signal is in its low voltage state, the second bipolar device having a emitter terminal coupled to the low voltage potential, a collector terminal coupled to the output terminal, and a base terminal coupled to the first bipolar device and biased by the bias signal of the low state voltage translation circuit;
• whereby current flowing through the voltage reducing circuit of the high state voltage translation circuit is higher when the first NMOS transistor is on enabling a higher current at the PMOS pull-up transistor and lower when the second NMOS transistor is on disabling the PMOS pull-up transistor.

A level shifter comprising:

• an input terminal for receiving an input signal having low and high voltage states;
• an output terminal for providing an output signal having low and high voltage states, wherein a voltage of the high voltage state of the output signal is different than a voltage of the high voltage state of the input signal;
• an inverter that receives the input signal and generates an internal control signal that represents an inversion of the input signal, wherein the inverter is powered by a low power supply voltage that generates a voltage approximately equivalent to a voltage of the high voltage state of the input signal such that a voltage of the internal control signal is approximately equivalent to the voltage of the high voltage state of the input signal;
• a low state voltage translation circuit generating a bias signal at a low state output node when the input signal is in its low voltage state, the low state voltage translation circuit receiving the internal control signal and comprising:
• a first NMOS transistor having its gate coupled to the internal control signal so that the first NMOS transistor is turned on when the input signal is in its low voltage state, its source terminal coupled to a low voltage potential, and its drain terminal coupled to the low state output node such that the bias signal is active when the first NMOS transistor is turned off;
• and
• a resistive network adapted to reduce current flowing to the low state output node;
• a high state voltage translation circuit coupled to a high power supply voltage and adapted to generate a high state control signal at a high state output node, wherein the high power supply voltage is approximately equivalent to the voltage of the high voltage state of the output signal, the high state voltage translation circuit comprising:
• a plurality of high state PMOS transistors connected in series and coupled to the high power supply voltage, the plurality of high state PMOS transistors arranged as a voltage reducing circuit with a voltage drop across each of the plurality of high state PMOS transistors approximately equal to each other and whereby each of the plurality of high state PMOS transistors reduces a voltage of the high power supply voltage;
• and
• an output stage providing the output signal comprising:
• a PMOS pull-up transistor connected the high power supply voltage and having its gate terminal coupled to the high state control signal to couple the high power supply voltage to the output terminal when the input signal is in its low voltage state to pull the output signal to its high voltage state, wherein a current flowing through the PMOS pull-up transistor approximately mirrors a current flowing through at least one of the plurality of high state PMOS transistors of the voltage reducing circuit of the high state voltage translation circuit;
• and
• a bipolar device adapted to pull the output signal to its low voltage state when the input signal is in its high voltage state, the bipolar device having an emitter terminal coupled to the low voltage potential, a collector terminal coupled to the output terminal, and a base terminal coupled to and biased by the bias signal of the low state voltage translation circuit.