Clock circuit for generating a delay
AssigneeCypress Semiconductor Corporation
InventorGalen E. Stansell
Life of this patent
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Abstract
A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.
Claims20
A circuit comprising:
- a circuit configured to generate a reference clock signal having a period;
- a divide circuit configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal;
- and
- an output circuit configured to generate (i) a first output clock signal in response to said first divided clock signal and said reference clock and (ii) a second output clock signal in response to said second divided clock signal, said reference clock signal and a digital complement of said reference clock signal, wherein said second output clock signal has a delay with respect to said first output clock signal and said delay is (i) a multiple of or (ii) a fraction of the period of said reference clock signal.
A circuit comprising:
- means for generating a reference clock signal having a period;
- means for generating a first divided clock signal and a second divided clock signal in response to said reference clock signal;
- and
- means for generating (i) a first output clock signal in response to said first divided clock signal and said reference clock and (ii) a second output clock signal in response to said second divided clock signal, said reference clock signal and a digital complement of said reference clock signal, wherein said second output clock signal has a delay with respect to said first output clock signal and said delay is (i) a multiple of or (ii) a fraction of the period of said reference clock signal.
A method for generating a delay comprising the step of:
- (A) generating a reference clock signal having a period;
- (B) generating a first divided clock signal and a second divided clock signal in response to said reference clock signal;
- and
- (C) generating (i) a first output clock signal in response to said first divided clock signal and said reference clock and (ii) a second output clock signal in response to said second divided clock signal, said reference clock signal and a digital complement of said reference clock signal, wherein said second output clock signal has a delay with respect to said first output clock signal, and said delay is (i) a multiple of or (ii) a fraction of the period of said reference clock signal.
Dependencies are inferred from the claim text.