Semiconductor integrated circuit having scan path
AssigneeFujitsu Limited
InventorKoichi Itaya
Life of this patent
Estimating the term…
Abstract
A logic circuit includes a combinational circuit 11 and a sequential circuit, outputs D0 to D3 of the combinational circuit 11 are provided to the respective data inputs D of flip-flops 12 to 15 of the sequential circuit through respective multiplexers 22 to 25, and the flip-flops 12 to 15 are cascaded through the multiplexers 22 to 25 to construct a scan path. AND gates 32 to 35 are provided for preventing changes in outputs of the flip-flops 12 to 15 from being transmitted to the combinational circuit 11 when the scan mode signal *SM is active, whereby the combinational circuit 11 is kept inoperative when data is serially transferred on the scan path consisting of the D flip-flops 12 to 15, an inverter 30 and the multiplexers 22 to 25.
Claims4
A semiconductor integrated circuit comprising a logic circuit, said logic circuit including a combinational circuit and a sequential circuit, said sequential circuit including a plurality of flip-flops and having normal and scan paths made selectively effective by a scan mode signal, said normal and scan paths being constructed in such a way that, when said scan mode signal is inactive, said flip-flops receive output data of said combinational circuit through respective multiplexers on input sides or in input stages of said flip-flops, and when said scan mode signal is active, said flip-flops are cascaded through said multiplexers to form a shift register, said semiconductor integrated circuit further comprising:
- a gate circuit for preventing an output of at least one of said flip-flops from being transmitted to said combinational circuit when said scan mode signal is active.
A semiconductor integrated circuit comprising a logic circuit, said logic circuit including a combinational circuit and a sequential circuit, said sequential circuit including a plurality of flip-flops and having normal and scan paths made selectively effective by a scan mode signal, said normal and scan paths being constructed in such a way that, when said scan mode signal is inactive, said flip-flops receive output data of said combinational circuit through respective multiplexers on input sides or in input stages of said flip-flops, and when said scan mode signal is active, said flip-flops are cascaded through said multiplexers to form a shift register, said semiconductor integrated circuit further comprising:
- a gate circuit for preventing an output of at least one of said flip-flops from being transmitted to succeeding one of said multiplexers when said scan mode signal is active.
Dependencies are inferred from the claim text.