US 6,271,692 B1 · Semiconductor integrated circuit

Abstract

An internal circuit of a semiconductor integrated circuit includes an inverter inputted with an input signal and is supplied with a power supply voltage during normal operation. The input terminal and the internal circuit are connected by a signal line having a resistor. A voltage determining circuit for determining whether a voltage of an input signal inputted to the input terminal is a signal voltage for use in the normal operation of the internal circuit or a high voltage for setting up an internal circuit test mode is connected to a node of the signal line. P-type MOS transistors are connected in series across a node of the signal line and the power supply voltage. The source of a first one of the P-type MOS transistors is connected to the power supply voltage together with the gate electrode and the substrate, and the drain is connected to the drain of the other P-type MOS transistor. The source of the other P-type MOS transistor is connected to the signal line together with the gate electrode and the substrate, and the drain is connected to the drain of the first P-type MOS transistor. An N-type MOS transistor is connected across the node of the signal line and the earth potential, the source is connected to the node of the signal line, and the drain is connected to the earth voltage together with the gate electrode and the substrate.

Claims19

Dependent claims

A semiconductor integrated circuit which receives an input signal and a test signal, the input signal having a first potential level and a second potential level which is lower than the first potential level, and the test signal having a third potential level which is higher than the first potential level, the semiconductor integrated circuit comprising:

an input terminal receiving the input signal and the test signal;
a first potential source supplying the first potential level;
a second potential source supplying the second potential level;
a first PMOS transistor coupled between said input terminal and said first potential source, wherein said first PMOS transistor turns on when said input terminal is at a first voltage which is higher than the third potential level;
a first NMOS transistor coupled between said input terminal and said second potential source, wherein said first NMOS transistor turns on when said input terminal is at a second voltage which is lower than the second potential level;
an internal circuit coupled to said input terminal, said internal circuit operating in response to the input signal and being in a test mode in response to a test mode signal;
and
a voltage determining circuit coupled to said input terminal and said internal circuit, said voltage determining circuit outputting the test mode signal in response to the test signal.

5 more elements

an input terminal receiving the input signal and the test signal;
a first potential source supplying the first potential level;
a second potential source supplying the second potential level;
a high voltage protection circuit coupled between said input terminal and said first potential source, wherein said high voltage protection circuit decreases an electric voltage that appears on said input terminal when said input terminal receives a high voltage signal having a first voltage which is higher than the third potential level;
a low voltage protection circuit coupled between said input terminal and said second potential source, wherein said low voltage protection circuit increases an electric voltage that appears on said input terminal when said input terminal receives a low voltage signal having a second voltage which is lower than the second potential level;
an internal circuit coupled to said input terminal, said internal circuit operating in response to the input signal and being in a test mode in response to a test mode signal;
and
a voltage determining circuit coupled to said input terminal and said internal circuit, said voltage determining circuit outputting the test mode signal in response to the test signal.

5 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims19