Method and apparatus for stalling OTB domino circuits

A processor, comprising:

• a clock generator to generate a plurality of clock signals;
• and
• a domino pipeline comprising:
• a plurality of first logic gates controlled by the plurality of clock signals, the plurality of first logic gates coupled in series and grouped to operate in a plurality of clock half cycles;
• and
• a logic block positioned at a start of one of the plurality of clock half cycle groups, the logic block comprising:
• a logic network having a plurality of inputs coupled to receive a plurality of input data signals, the logic network to generate an output signal on an output node based on a logic evaluation of the plurality of input data signals;
• a first transistor coupled to the output node to precharge the output node and a second transistor coupled to the logic network;
• and
• a feedback circuit coupled to the logic network to maintain the output signal on the output node based on a stall input signal.

A method for stalling data, comprising:

• receiving the plurality of data input signals at a plurality of first inputs of a logic block, the logic block having a second input, a stall input, and an output;
• generating a first output signal on the output of the logic block based on a logic evaluation of the first plurality of inputs during a first clock cycle;
• receiving a stall signal at the stall input of the logic block;
• recirculating the first output signal to the second input of the logic block during the first clock cycle;
• and
• transmitting the output signal received at the second input to the output of the logic block based on a stall signal.