Dynamic logic scan gate method and apparatus

A scannable logic circuit system, comprising:

• a clocked precharge logic circuit that includes a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers, said logic circuit receives a clock signal and one or more input signals and produces one or more output signals;
• a scan control circuit that generates scan control signals, said scan control signals further comprise a scan enable signal;
• one or more scan registers;
• one or more read/write drivers;
• and
• one or more scan circuits, each said scan circuit couples to one of said output buffers and to one of said scan registers through one of said read/write drivers, each said scan circuit receives said scan control signals from said scan control circuit, provides the state of said output signal to said scan register, and forces said output signal to a state specified by information in said scan register.

A method to make a scannable logic circuit apparatus, comprising:

• providing a clocked precharge logic circuit that includes a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers, said logic circuit receives a clock signal and one or more input signals and produces one or more output signals;
• providing a scan control circuit that generates scan control signals, said scan control signals further comprise a scan enable signal;
• providing one or more scan registers;
• providing one or more read/write drivers;
• and
• providing one or more scan circuits, each said scan circuit couples to one of said output buffers and to one of said scan registers through one of said read/write drivers, each said scan circuit receives said scan control signals from said scan control circuit, provides the state of said output signal to said scan register, and forces said output signal to a state specified by information in said scan register.

A scan method that reads the output state of a logic circuit, comprising:

• generating one or more output signals from one or more input signals and one or more clock signals provided to a clocked precharge logic circuit that includes a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers;
• generating scan control signals, said scan control signals further comprise a scan enable signal, a read signal, and one or more write signals;
• preventing the state of said output signal from changing when said input signals change;
• providing said read signal to one or more scan circuits, wherein each said scan circuit is coupled to one of said output buffers;
• and
• providing said read signal to one or more read/write drivers, wherein each said read/write driver couples to one of said scan circuits and to a scan register.

A scan method that forces the output state of a logic circuit to a user-selected state, comprising:

• loading a scan register with the user-selected output state of a clocked precharge logic circuit that includes a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers;
• generating scan control signals, said scan control signals further comprise a read signal, one or more write signals, and a scan enable signal;
• precharging said evaluate nodes;
• preventing said evaluate circuit from evaluating said logic tree;
• providing said one or more write signals to one or more scan circuits, wherein each said scan circuit is coupled to one of said output buffers;
• and
• providing said one or more write signals to one or more read/write drivers, wherein each said read/write driver is coupled to said scan register and to one of said scan circuits.