Semiconductor integrated circuit and method for testing the semiconductor integrated circuit

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• path selection step of selecting an untested signal transmission path which has not yet been subjected to the test, as a target signal transmission path, from a predetermined number of signal transmission paths to be subjected to the test which are positioned between said two registers;
• delay decision step of inputting the timing signal to registers on the starting point side and the end point side of the target signal transmission path, at an interval according to a delay time on design which is set for the target signal transmission path, and detecting whether or not a test signal generated in the starting-point-side register has been transmitted to the end-point-side register within the delay time on design, and deciding that the target signal transmission path is an already-tested signal transmission path;
• fault decision step of deciding that the semiconductor IC has a fault in the target signal transmission path and terminating the test when the test signal has not reached the end-point-side register within the delay time on design, and deciding that all of partial paths which are components of the target signal transmission path and are separated by a logic element on the path, are not faulty when the test signal has reached the end-point-side register within the delay time on design;
• and
• already-tested-path decision step of deciding that, amongst the plural signal transmission paths to be subjected to the test, an untested signal transmission path comprising only the partial paths which have been decided as being not faulty is an already-tested signal transmission path for which no test is required;
• wherein said path selection step, said delay decision step, said fault decision step, and said tested-path decision step are repeated until all of the predetermined number of signal transmission paths to be subjected to the test have been decided as already-tested signal transmission paths.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• delay decision step of detecting whether or not a test signal generated in a starting-point-side register of a target signal transmission path to be subjected to the test has been transmitted to an end-point-side register within an allowable delay time based on the performance of the semiconductor IC on design;
• maximum delay time derivation step of deriving maximum delay times for partial paths which are components of the target signal transmission path and are separated by a logic element on the path, on the basis of the allowable delay time and the delay times of the respective partial paths on design, when the test signal has reached the end-point-side register within the allowable delay time;
• and
• already-tested-path decision step of deciding that an untested signal transmission path which comprises only the partial paths to which the maximum delay times are assigned and has the sum of the maximum delay times of the respective partial paths being shorter than the allowable delay time, is an already-tested signal transmission path for which no test is required.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• path selection step of selecting an untested signal transmission path which has not yet been subjected to the test, as a target signal transmission path, from a predetermined number of signal transmission paths to be subjected to the test which are positioned between said two registers;
• delay decision step of detecting whether or not a test signal generated in a starting-point-side register of the target signal transmission path has been transmitted to an end-point-side register within an allowable delay time based on the performance of the semiconductor IC on design, and deciding that the target signal transmission path is an already-tested signal transmission path;
• maximum delay time derivation step of deciding that the semiconductor IC has a fault in the target signal transmission path and terminating the test when the test signal has not reached the end-point-side register within the allowable delay time, and deriving maximum delay times for partial paths which are components of the target signal transmission path and are separated by a logic element on the path, on the basis of the allowable delay time and the delay times of the respective partial paths on design, when the test signal has reached the end-point-side register within the allowable delay time;
• delay time assignment step of assigning the derived maximum delay time to the partial path whose maximum delay time derived is smaller than a maximum delay time which has already been assigned or to the partial path to which no maximum delay time has not yet been assigned, amongst the partial paths constituting the target signal transmission path;
• and
• already-tested-path decision step of deciding that, amongst the plural signal transmission paths to be subjected to the test, an untested signal transmission path which comprises only the partial paths to which the maximum delay times are assigned and has the sum of the maximum delay times of the respective partial paths being shorter than the allowable delay time is an already-tested signal transmission path for which no test is required;
• wherein said path selection step, said delay decision step, said maximum delay time derivation step, said delay time assignment step, and said already-tested-path decision step are repeated until all of the predetermined number of signal transmission paths to be subjected to the test have been regarded as already-tested signal transmission paths.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• delay decision step of selecting a clock signal as said timing signal from plural clock signals having different cycles, said clock signal having a minimum cycle that is not shorter than a delay time on design which is set for a target signal transmission path to be subjected to the test, and inputting the timing signal to registers on the starting point side and the end point side of the target signal transmission path, and detecting whether or not a test signal generated in the starting-point-side register of the target signal transmission path has been transmitted to the end-point-side register within the minimum cycle;
• maximum delay time derivation step of deriving maximum delay times for partial paths which are components of the target signal transmission path and are separated by a logic element on the path, on the basis of the minimum cycle and the delay times of the respective partial paths on design, when the test signal has reached the end-point-side register within the minimum cycle;
• and
• already-tested-path decision step of deciding that an untested signal transmission path which comprises only the partial paths to which the maximum delay times are assigned and has the sum of the maximum delay times of the respective partial paths being shorter than an allowable delay time based on the performance of the semiconductor IC on design, is an already-tested signal transmission path for which no test is required.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• path selection step of selecting an untested signal transmission path which has not yet been subjected to the test, as a target signal transmission path, from a predetermined number of signal transmission paths to be subjected to the test, positioned between said two registers;
• delay decision step of selecting a clock signal as said timing signal from plural clock signals having different cycles, said clock signal having a minimum cycle that is not shorter than a delay time on design which is set for the target signal transmission path, and inputting the timing signal to registers on the starting point side and the end point side of the target signal transmission path, and then detecting whether or not a test signal generated in the starting-point-side register of the target signal transmission path has been transmitted to the end-point-side register within the minimum cycle, and thereafter, deciding that the target signal transmission path is an already-tested signal transmission path;
• maximum delay time derivation step of deciding that the semiconductor IC has a fault in the target signal transmission path and terminating the test when the test signal has not reached the end-point-side register within the minimum cycle, and deriving maximum delay times for partial paths which are components of the target signal transmission path and are separated by a logic element on the path, on the basis of the minimum cycle and the delay times of the respective partial paths on design, when the test signal has reached the end-point-side register within the minimum cycle;
• delay time assignment step of assigning the derived maximum delay time to the partial path whose maximum delay time derived is smaller than a maximum delay time which has already been assigned or to the partial path to which no maximum delay time has not yet been assigned, amongst the partial paths constituting the target signal transmission path;
• and
• already-tested-path decision step of deciding that, amongst the plural signal transmission paths to be subjected to the test, an untested signal transmission path which comprises only the partial paths to which the maximum delay times are assigned and has the sum of the maximum delay times of the respective partial paths being shorter than an allowable delay time based on the performance of the semiconductor IC on design, is an already-tested signal transmission path for which no test is required;
• wherein said path selection step, said delay decision step, said maximum delay time derivation step, said delay time assignment step, and said already-tested-path decision step are repeated until all of the predetermined number of signal transmission paths to be subjected to the test have been regarded as already-tested signal transmission paths.

A semiconductor IC having a plurality of registers which hold input signals according to a timing signal, and a logic circuit which includes a plurality of signal transmission paths and exchanges signals with predetermined registers,

• said logic circuit including:
• a plurality of signal transmission paths positioned between predetermined two registers;
• a logic element forming a re-convergence point at which part or all of the plural signal transmission paths re-converge between said two registers;
• one of said two registers being a starting-point-side register which generates a test signal when performing detection of faults in the signal transmission paths while the other register being an end-point-side register which receives the test signal output from the starting-point-side register through the signal transmission paths;
• and
• said logic element being connected with either or both of an additional starting-point-side register which outputs a test signal to the logic element when performing detection of faults in the signal transmission paths and an additional end-point-side register which receives the test signal output from the logic element.

A semiconductor IC having a plurality of registers which hold input signals according to a timing signal, and a logic circuit which includes a plurality of signal transmission paths and exchanges signals with predetermined registers,

• said logic circuit including:
• a plurality of signal transmission paths positioned between predetermined two registers;
• a logic element forming a re-convergence point at which part or all of the plural signal transmission paths re-converge between the two registers;
• and
• one of the two registers being a starting-point-side register which generates a test signal when performing detection of faults in the signal transmission paths while the other register being an end-point-side register which receives the test signal output from the starting-point-side register through the signal transmission paths;
• and
• said semiconductor IC further including:
• a test timing generator for generating a test clock for deciding a timing at which the starting-point-side register generates the test signal and a timing at which the end-point-side register observes the test signal, and outputting the test clock to the respective registers;
• and
• said test timing generator generating a test clock of a predetermined frequency on the basis of a timing selection signal supplied from the outside.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• preliminary test step of performing a preliminary test on a pseudo semiconductor IC which is constituted by a computer and has the same structure as that of the semiconductor IC;
• and
• regular test step of performing a regular test on the real semiconductor IC, on the basis of the result of the preliminary test;
• said preliminary test step including:
• path selection step of selecting an untested signal transmission path which has not yet been tested, as a target signal transmission path, from a predetermined number of signal transmission paths to be tested which are positioned between two registers in the pseudo semiconductor IC;
• and
• decision step of deciding that all of partial paths which are components of the target signal transmission path and are separated at a logic element on the path, have no faults, and deciding that an untested signal transmission path comprising only the partial paths having no faults is an already-tested signal transmission path for which no test is required;
• and
• said regular test step including:
• delay decision step of inputting a timing signal to registers on the starting point side and the end point side of a signal transmission path in the real semiconductor IC, which corresponds to a signal transmission path in the pseudo semiconductor IC other than the signal transmission path that has been decided as an already-tested path in the decision step of the preliminary test, at an interval according to a delay time on design which is set for the signal transmission path, and detecting whether or not a test signal generated in the starting-point-side register has been transmitted to the end-point-side register within the delay time on design.

A method for subjecting a semiconductor IC which has a plurality of registers holding input signals according to a timing signal, and a logic circuit including a plurality of signal transmission paths and exchanging signals with predetermined registers, to a test for detecting faults in plural signal transmission paths positioned between two registers, said method comprising:

• preliminary test step of performing a preliminary test on a pseudo semiconductor IC which is constructed by a computer and has the same structure as that of the semiconductor IC;
• and
• regular test step of performing a regular test on the real semiconductor IC, on the basis of the result of the preliminary test;
• said preliminary test step including:
• path selection step of selecting an untested signal transmission path which has not yet been tested, as a target signal transmission path, from a predetermined number of signal transmission paths to be tested which are positioned between two registers in the pseudo semiconductor IC;
• and
• maximum delay time derivation step of deriving maximum delay times for partial paths which are components of the target signal transmission path and are separated by a logic element on the path, on the basis of an allowable delay time based on the performance of the semiconductor IC and the delay times of the respective partial paths on design;
• and
• decision step of deciding that an untested signal transmission path which comprises only the partial paths to which the maximum delay times are assigned and has the sum of the maximum delay times of the partial paths being shorter than the allowable delay time, is an already-tested signal transmission path for which no test is needed;
• and
• said regular test step including:
• delay decision step of inputting a timing signal to registers on the starting point side and the end point side of a signal transmission path in the real semiconductor IC, which corresponds to a signal transmission path in the pseudo semiconductor IC other than the signal transmission path that has been decided as an already-tested path in the decision step of the preliminary test, at an interval according to an allowable delay time based on the performance on design which is set for the signal transmission path, and detecting whether or not a test signal generated in the starting-point-side register has been transmitted to the end-point-side register within the allowable delay time.