Terminal contact-type IC card having terminal contact fault detector, IC card system using the IC card, and IC for the IC card

An integrated circuit for an IC card having a first reset terminal configured such that it can be connected with a second reset terminal of an external unit, the external unit having a pull-up resistor connected between a first high-level power supply and the second reset terminal, the integrated circuit comprising:

• (a) a central processing unit (CPU);
• (b) a detector connected to the CPU and configured such that it can bc connected to the first reset terminal, the detector providing a faulty contact indicating signal to the CPU when a contact between the first and second reset terminals is faulty;
• and
• (c) a memory connected to the CPU.

An integrated circuit for an IC card having a first clock terminal configured such that it can be connected with a second clock terminal of an external unit, the integrated circuit comprising:

• (a) a central processing unit (CPU);
• (b) a detector connected to the CPU and configured such that it can be connected to the first clock terminal, comprising:
• a first input circuit configured such that it can be connected to the first clock terminal, an inverter circuit connected to the first clock terminal,
• a selector configured such that it can be connected to the first clock terminal,
• a second input circuit connected to the inverter circuit, and
• a confirmation gate circuit connected to the first and second input circuits;
• and
• (c) a memory connected to the CPU.

An IC card having a first reset terminal configured such that it can be connected with a second reset terminal of an external unit, the IC card comprising:

• (a) a peripheral circuit having a memory;
• (b) a central processing unit (CPU) notifying of an abnormal contact between the first and second reset terminals to the external unit, and controlling the operation of the peripheral circuit upon receiving a command from the external unit;
• and
• (c) a detector connected between the CPU and the first reset terminal, and configured such that it can test the abnormal contact between the first and second reset terminals, upon receiving a signal supplied by the CPU.

An IC card having a first reset terminal configured such that it can be connected with a second reset terminal of an external unit, comprising:

• (a) a central processing unit (CPU) testing whether the first reset terminal is connected to the second reset terminal, notifying to the external unit of a faulty contact if the first reset terminal is not sufficiently connected to the second reset terminal, and prohibiting the resetting of the CPU while testing and notifying;
• (b) a detector connected between the CPU and the first reset terminal and configured to detect a variation of a potential at the first reset terminal upon receiving input signals supplied by the CPU;
• and
• (c) a memory connected to the CPU.

An IC card having a first reset terminal configured such that it can be connected with a second reset terminal of an external unit, comprising:

• (a) a central processing unit (CPU) testing whether the first reset terminal is connected to the second reset terminal, notifying to the external unit of a faulty contact if the first reset terminal is not sufficiently connected to the second reset terminal, and continuing to complete an access operation, which is in progress when the first reset terminal is not sufficiently connected to the second reset terminal, and then, stopping the operation of the CPU;
• (b) a detector connected between the CPU and the first reset terminal;
• and
• (c) a memory connected to the CPU.

An IC card having a first clock terminal configured such that it can be connected with a second clock terminal of an external unit, the integrated circuit comprising:

• (a) a central processing unit (CPU) testing whether the first clock terminal is connected to the second clock terminal, and continuing to complete an access operation under progress even when an abnormal contact between the first and second clock terminals is observed;
• (b) a detector connected between the CPU and the first clock terminal and configured to detect a pulse waveform at a node in the detector to provide an output signal to the CPU;
• and
• (c) a memory connected to the CPU.

An IC card system comprising:

• (a) an IC card having,
• a first reset terminal memory,
• a central processing unit (CPU) connected to the memory, and
• a detector connected between the CPU and the first reset terminal, and configured to detect a variation of a potential at the first reset terminal for testing an abnormal contact upon receiving a signal supplied by the CPU;
• and
• (b) an external unit comprising,
• a second reset terminal to be connected with the first reset terminal, and
• a pull-up resistor connected between a first high-level power supply and the second reset terminal.

An IC card system comprising:

• (a) an IC card comprising
• a first reset terminal,
• a central processing unit (CPU) testing a contact condition of the first reset terminal by notifying a detector connected between the CPU and the first reset terminal to detect the contact condition, notifying of a faulty contact if the contact condition detected by the detector is faulty, and prohibiting the resetting of the CPU while testing, and
• a memory connected to the CPU;
• and
• (b) an external unit having a second reset terminal configured to be connected with the first reset terminal, said CPU configured to notify the external unit of the faulty contact between the first and second reset terminals, when the faulty contact is detected by the detector.

An IC card system comprising:

• (a) an IC card comprising:
• a first reset terminal;
• a central processing unit (CPU) testing a contact condition to the first reset terminal, notifying of a faulty contact if the contact condition is faulty, and continuing to complete an access operation, which is in progress when the contact condition is faulty, and then, stopping the operation of the CPU;
• a detector connected between the CPU and the first reset terminal;
• and
• a memory connected to the CPU;
• and
• (b) an external unit having a second reset terminal to be connected with the first reset terminal, said CPU configured to notify the external unit of the faulty contact between the first and second reset terminals.

An integrated circuit for an IC card having a first clock terminal configured such that it can be connected to a second clock terminal of an external unit, the integrated circuit comprising:

• (a) a memory;
• (b) a central processing unit (CPU) connected to the memory;
• (c) a detector connected to the CPU and configured such that it can be connected to the first clock terminal and configured such that it can detect a pulse waveform at a node in the detector for testing an abnormal contact between the first and second clock terminals;
• and
• (d) a self oscillator connected between the CPU and the detector.

An IC card system comprising:

• (a) an IC card comprising:
• a first clock terminal,
• a memory,
• a central processing unit (CPU) connected to the memory,
• a detector connected between the CPU and the first clock terminal and configured to detect a pulse waveform at a node in the detector for testing an abnormal contact upon receiving a signal supplied by the CPU, and
• a self oscillator connected between the CPU and the detector;
• and
• (b) an external unit having a second clock terminal to be connected with the first clock terminal,
• wherein the abnormal contact between the first and second clock terminals is detected by the detector.