Connection arrangement for enbaling the use of identical chips in 3-dimensional stacks of chips requiring address specific to each chip

Abstract

An integrated circuit having first and second identical layers of circuitry. Each layer includes a substrate having a plurality of components thereon. Each layer also includes circuit selection circuitry for enabling the integrated circuit components on that layer to perform a predetermined function. The circuit selection circuitry includes a circuit selection terminal for receiving a signal that enables the predetermined function. Each layer also includes N input pads and N output pads, where N>1. The input and output pads are labeled from 1 to N. Each input pad is connected to a corresponding one of the output pads. The connection scheme is chosen such that there is a one-to-one mapping between the input pads and the output pads and no input pad is connected to an output pad on that layer having the same label as the input pad. The circuit selection terminal is connected to a predetermined one of the input pads. The layers are connected such that the input pad labeled k on the second layer is connected to the output pad labeled k on the first layer for k=1 to N.

Dependencies are inferred from the claim text.