Uprom memory cells for non-volatile memory devices integrated on semiconductors
AssigneeSTMicroelectronics S.r.l.
InventorsSalvatore Polizzi, Marco Lauricella
Life of this patent
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Abstract
A redundancy UPROM cell includes at least one memory element of EPROM or Flash type, having a control terminal and a conduction terminal to be biased, an inverter register connected to the memory element by at least one MOS transistor. Such cell also includes a pass transistor which connects said conduction terminal to a data line and a pull-up transistor which connects the data line to a supply voltage reference. The UPROM cell has the great advantage to result in smaller dimensions in comparison with the cells of known type, at equal final functions and performances being assumed.
Claims22
A redundancy UPROM cell, comprising a memory element of EPROM or Flash type having a power terminal and a conduction terminal to be driven, the UPROM cell including an inverter register connected to the memory element by a MOS transistor;
- and a pass transistor which connects said conduction terminal to a data line.
A non-volatile memory cell matrix, comprising:
- a first group of memory cells each including a memory element and a register having an input and an output, the output being coupled to the memory element;
- a first data line coupled to each memory cell of the first group;
- and
- a first pull-up transistor coupling the first data line to a supply voltage reference.
A method of controlling a redundancy memory cell that includes a memory element and a register, the method comprising:
- resetting the register by coupling an input of the register to a data line carrying a reset signal;
- and
- programming the memory element by coupling the data line to a conductive terminal of the memory element and driving a high voltage programming signal on the data line to the conductive terminal.
A redundancy UPROM cell, comprising:
- a non-volatile memory element having a conduction terminal and a control terminal;
- a data latch register having an input terminal coupled to the conduction terminal of the memory element by a first MOS transistor, and having an output terminal coupled to a data line;
- and
- a pass transistor having a first conduction terminal coupled to the data line and having a second terminal coupled to the conduction terminal of the memory element.
A non-volatile memory matrix grouped into at least a first and a second sector, the matrix comprising:
- a plurality of UPROM cells, each cell including:
- a non-volatile memory element having a conduction terminal,
- a data register coupled to the conduction terminal of the non-volatile memory element and having an output terminal, and
- a pass transistor coupled between the output terminal and the conduction terminal of the non-volatile memory element;
- a first data line coupled to the output terminal of one of the UPROM cells in the first sector and coupled to the output terminal of one of the UPROM cells in the second sector;
- a first pull-up transistor coupling the first data line to a supply voltage reference;
- a second data line coupled to the output terminal of a second one of the UPROM cells in the first sector and coupled to the output terminal of a second one of the UPROM cells in the second sector;
- and
- a second pull-up transistor coupling the second data line to the supply voltage reference.
Dependencies are inferred from the claim text.