Semiconductor device having memory cells and method of manufacturing the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYoshiyuki Ishigaki, Hiroki Honda
Life of this patent
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Abstract
According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.
Claims16
A semiconductor device comprising:
- a plurality of memory cells, each of said memory cells comprising:
- a first interconnection layer formed on a semiconductor substrate, and including a high-resistance interconnection portion and a storage node portion, said high-resistance interconnection portion comprised of separate first and second portions, said first interconnection layer further including a power supply interconnection portion comprised of separate first and second portions respectively connected to the first and second portions of said high resistance interconnection portion;
- a GND interconnection layer formed on said first interconnection layer with a dielectric film therebetween, wherein
- said storage node portion of said first interconnection layer, said GND interconnection layer and said dielectric film form a capacitor element, and
- said first interconnection layer is arranged symmetrically around a center of said memory cell;
- and
- a second interconnection layer including a gate electrode, formed on said semiconductor substrate and located under said first interconnection layer;
- and wherein
- memory cells formed next to each other in a direction of a word line have the same planar layout,
- the first portion of the high resistance interconnection portion of one memory cell, the first portion of the high resistance interconnection of another memory cell adjacent the one memory cell, and the first portion of the power supply interconnection connected to these first portions of the high resistance interconnection portion form a closed end area surrounded at three sides thereof,
- said first interconnection layer includes a lower layer in contact with said semiconductor substrate and said second interconnection layer, and an upper layer formed on said lower layer, and
- said GND interconnection layer covers side surfaces of said lower and upper layers with said dielectric film therebetween, and
- the closed end area has an opening divided into two parts by the second portion of the high resistance interconnection portion of the one memory cell.
Dependencies are inferred from the claim text.