Semiconductor device with high gettering capability to impurity present in semiconductor layer of SOI substrate

A semiconductor device comprising:

• a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order;
• a transistor which is disposed in an element formation region of said SOI substrate and has a channel formation region selectively disposed in a main surface of said semiconductor layer, a gate insulating film on said channel formation region, a gate electrode on said gate insulating film, and source/drain regions disposed in said main surface of said semiconductor layer and adjacent said channel formation region;
• and
• a polycrystal semiconductor region selectively disposed such as to make no contact with said gate insulating film, on part of said main surface of said semiconductor layer where said source/drain regions are disposed.

A semiconductor device comprising:

• a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and a semiconductor layer are stacked in this order;
• a trench-type element isolation insulating film disposed in a main surface of said semiconductor layer such as not to reach said insulating layer, in an element isolation region of said SOI substrate;
• and
• a crystal defect region locally disposed in part of said semiconductor layer where said element isolation insulating film is not disposed, in said element isolation region of said SOI substrate.

A semiconductor device comprising:

• a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order;
• a transistor which is disposed in an element formation region of said SOI substrate and having a channel formation region selectively disposed in a main surface of said semiconductor layer, a gate insulating film on said channel formation region, a gate electrode on said gate insulating film, and source/drain regions disposed in said main surface of said semiconductor layer and adjacent said channel formation region;
• and
• a first polycrystal semiconductor region selectively extending through said insulating layer between an upper surface of said insulating layer and a bottom surface of said insulating layer, beneath the source/drain regions.