Multi-step plasma process for forming TiSiN barrier

A method for fabricating a TiSiN metal diffusion barrier layer for integrated circuits on a substrate with single or dual damascene structures comprising:

• providing a substrate or wafer having an insulator layer of silicon dioxide deposited upon said substrate;
• providing a first level of copper conducting wiring over said insulator layer;
• depositing a first and second dielectric layer over said first level of conducting wiring;
• patterning and etching the dielectric layers forming both single and dual damascene trench/via structure openings for interconnects and contact vias;
• heating up said substrate or wafer;
• depositing by metal-organic chemical vapor deposition (MOCVD), a diffusion barrier layer of TiNxCyOz, TiCxNyHz, type complexes over said dielectric layers covering and lining said trench/via openings;
• exposing the of TiNxCyOz, TiCxNyHz, type complexes which form the diffusion barrier layer to a N2, H2 gas plasma forming a TiN diffusion barrier layer;
• exposing the said barrier layer to a silane gas plasma enhanced deposition injecting silicon into said barrier layer forming a TiSiN barrier layer;
• vacuum pumping and purging removing unwanted byproducts from said TiSiN barrier layer and from said substrate or wafer, by placement of said substrate or wafer in a vacuum chamber;
• depositing by chemical vapor deposition a copper seed layer over said diffusion barrier layer;
• depositing by electrochemical deposition (ECD) copper conducting material over the said copper seed layer and said barrier layer and removing the excess material layers, excess copper and excess barrier layer material, by planarizing the surface by chemical mechanical polish (CMP) to form conducting copper dual inlaid structures which are conducting interconnect lines and contact vias.

A method for fabricating MOSFET and CMOS devices on a silicon semiconductor substrate with single or dual damascene structures using electrochemical deposition (ECD) of copper and chemical vapor deposition (CVD) of copper seed layer on a multi-step plasma treated TiSiN metal diffusion barrier layer, comprising:

• providing a substrate or wafer having an insulator layer of silicon dioxide deposited upon said substrate;
• providing a first level of copper conducting wiring over said insulator layer;
• depositing a first and second dielectric layer over said first level of conducting wiring;
• patterning and etching the dielectric layers forming both single and dual damascene trench/via structure openings for interconnects and contact vias;
• heating up said substrate or wafer;
• depositing by metal-organic chemical vapor deposition (MOCVD), a diffusion barrier layer of TiNxCyOz, TiCxNyHz, type complexes over said dielectric layers covering and lining said trench/via openings;
• exposing the of TiNxCyOz, TiCxNyHz, type complexes which form the diffusion barrier layer to a N2, H2 gas plasma forming a TiN diffusion barrier layer;
• exposing the said barrier layer to a silane gas plasma enhanced deposition injecting silicon into said barrier layer forming a TiSiN barrier layer;
• vacuum pumping and purging removing unwanted byproducts from said TiSiN barrier layer and from said substrate or wafer, by placement of said substrate or wafer in a vacuum chamber;
• depositing by chemical vapor deposition a copper seed layer over said diffusion barrier layer;
• depositing by electrochemical deposition (ECD) copper conducting material over the said copper seed layer and said barrier layer and removing the excess material layers, excess copper and excess barrier layer material, by planarizing the surface by chemical mechanical polish (CMP) to form conducting copper dual inlaid structures which are conducting interconnect lines and contact vias.