Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication

A method of fabricating Field Effect Transistor (FET's) having low sheet resistance gate electrodes comprising the steps of:

• providing a semiconductor substrate;
• forming shallow trench isolation areas surrounding and electrically isolating device areas;
• depositing a polysilicon layer on said substrate;
• depositing a layer of titanium nitride on said polysilicon layer;
• patterning said titanium nitride layer and said polysilicon layer by photoresist masking and anisotropic etching thereby forming said gate electrodes and leaving portions over the top of said gate electrodes;
• forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;
• depositing a conformal dielectric layer over said gate electrode and the surface of said substrate;
• anisotropically etching back said conformal dielectric layer thereby forming sidewall spacers on said gate electrode;
• forming source/drain contact areas by ion implantation adjacent to said sidewall spacers;
• depositing a blanket layer of titanium (Ti) over said gate electrode and the areas adjacent to said gate electrode thereby including said shallow trench isolation regions;
• annealing said titanium to form titanium silicide (TiSi2) on said source/drain contact areas thereby leaving unreacted titanium on the insulated surfaces of said substrate;
• stripping said unreacted titanium from said substrate;
• stripping said portions from said top of said gate electrodes thereby forming a recessed gate electrode;
• depositing a blanket layer of cobalt (Co) over said stripped portion of said gate electrode thereby including the exposed portions of said spacers thereby further including the surface of said substrate adjacent to said gate electrode;
• annealing said cobalt to form CoSi2 over said gate;
• and
• removing selectively said cobalt layer over said gate electrodes by wet etching while leaving the layer of formed CoSi2 on said top surface of said gate electrode.

A method for forming a transistor comprising the steps of:

• providing a semiconductor substrate;
• forming shallow trench isolation (STI) regions within said substrate said STI's bordering on and delineating said transistor;
• forming a gate electrode overlying said substrate and within the area delineated by said STI's said gate electrode having a lower layer containing polysilicon and an upper layer containing a dielectric material that functions as a masking layer;
• forming sidewall spacers that are laterally adjacent to said gate electrodes;
• forming source and drain regions within said substrate and adjacent to said gate electrode;
• depositing a layer of titanium over said electrode thereby including said gate spacers and the area adjacent to said gate electrode including said STI's;
• annealing said deposited layer of titanium with said substrate over the source and drain regions thereby forming thin layers of TiSi2 over these regions;
• removing selectively said unreacted titanium thereby also removing said upper layer of said gate electrode;
• depositing a blanket layer of cobalt over said the exposed poly surface of said gate electrode including said gate spacers and the areas adjacent to said electrode further including said STI areas;
• annealing said cobalt thereby forming a reactive layer of CoSi2 on the surface of the poly layer of said gate electrode;
• and
• selectively removing unreacted cobalt thereby exposing said TiSi2 layers over said source and drain regions thereby further exposing the layer of CoSi2 on the top surface of said gate electrode.