Self-aligned source and drain extensions fabricated in a damascene contact and gate process
AssigneeAdvanced Micro Devices, Inc.
InventorsQi Xiang, Matthew S. Buynoski, Ming-Ren Lin
Life of this patent
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Abstract
A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.
Claims20
A process for fabricating an integrated circuit, comprising:
- (a) forming a polysilicon masking pattern on a substrate, the masking pattern having a first spacing between a gate region and a first contact region and a second spacing between the gate region and a second contact region, the polysilicon masking pattern covering the gate region, the first contact region, and the second contact region;
- (b) forming a shallow source region below the first spacing and a shallow drain region below the second spacing;
- (c) depositing an insulative material in the first spacing and the second spacing;
- (d) removing the polysilicon masking pattern, thereby leaving the insulative material in the first spacing and the second spacing and exposing the substrate at the first contact region and the second contact region;
- (e) providing a photoresist over the gate region;
- (f) forming a deep source region at the first contact region and a deep drain region at the second contact region;
- (g) removing the photoresist;
- and
- (h) depositing a gate dielectric and a gate conductor over the gate region.
A method of fabricating an integrated circuit on a substrate including a shallow source region below a first insulative structure and a shallow drain region below a second insulative structure, the substrate having a first conductive structure separated from a second conductive structure by the first insulative structure, the substrate having a third conductive structure separated from the second conductive structure by the second insulative structure, the second conductive structure being at a gate location, the method comprising:
- removing the first conductive structure and the third conductive structure to expose a first substrate region and a third substrate region;
- doping the substrate to form a deep source region and a deep drain region within the first substrate region and the third substrate region;
- removing the second conductive structure to expose a second substrate region;
- and
- providing a gate conductor over the second substrate region corresponding to the gate location.
A damascene method of fabricating an integrated circuit on a substrate, the substrate having a first conductive structure separated from a second conducive structure by a first space, the substrate having a third conductive structure separated from the second conductive structure by a second space, the second conductive structure being at a gate location, the method comprising steps of:
- forming a shallow source region below the first space and a shallow drain region below the second space;
- depositing an insulative material in the first space and the second space;
- removing the first conductive structure and the third conductive structure;
- forming a deep source region and a deep drain region in regions of the substrate exposed by the removing step;
- removing the second conductive structure;
- and
- depositing a gate conductor over the gate location.
Dependencies are inferred from the claim text.