Method of making a dynamic random access memory device utilizing chemical mechanical polishing

A method for fabricating a semiconductor memory device with a capacitor-over-bit line structure, comprising the steps of:

• forming a first transistor having a first gate electrode and a second transistor having a second gate electrode on a semiconductor substrate;
• wherein the first and second transistors share a conductive region formed in the substrate between the first and second gate electrodes;
• covering the first and second gate electrodes and the conductive region with a first insulating layer;
• forming a first opening in the first insulating layer and exposing at least a portion of the conductive region;
• forming a conductive pad in communication with the conductive region in the substrate via the first opening;
• forming a second insulating layer over the first and second gate electrodes and the conductive pad;
• forming a second opening in the second insulating layer and exposing the conductive pad;
• forming a conductive stepped bit line over the second insulating layer and in communication with the conductive pad via the second opening, the stepped bit line having a portion above the transistor that is raised relative to the substrate;
• depositing a third stepped insulating layer over the second insulating layer and the bit line;
• planarizing the third insulating layer and exposing a portion of the bit line using a chemical mechanical polishing step;
• forming a fourth insulating layer over the third insulating layer and the exposed portion of the bit line;
• and
• forming a capacitor over the fourth insulating layer.