Interlayer between titanium nitride and high density plasma oxide
AssigneeAdvanced Micro Devices, Inc.
InventorsChristopher L. Wooten, Craig W. Christian, Thomas E. Spikes, Jr., Allen L. Evans, Tim Z. Hossain
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Abstract
A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.
Claims27
A method for fabricating a multilevel interconnect structure of an integrated circuit comprising:
- forming at least one conductive line above the surface of a semiconductor substrate;
- forming a first layer comprised of a non-HDP dielectric material above the surface of the semiconductor substrate;
- forming a second layer comprised of a high density plasma oxide above the first layer;
- forming a via above said at least one conductive line;
- depositing a layer of titanium at least within said via;
- depositing a layer of titanium nitride above said layer of titanium in said via;
- and
- filling the via with a conductive material.
A method for reducing die loss in a process in which HDP oxide and titanium nitride are in contact above a semiconductor substrate, which process comprises providing between said HDP oxide layer and said titanium nitride layer a non-HDP dielectric interlayer.
Dependencies are inferred from the claim text.