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US 6,271,107 B1Granted
Semiconductor with polymeric layer
AssigneeFujitsu Limited
InventorsThomas Massingill, Mark Thomas McCormack, Hunt Hang Jiang
Life of this patent
Estimating the term…
Abstract
Bumped semiconductor substrates and methods for forming bumped semiconductor substrates are disclosed. The bumped semiconductor substrates have a polymeric layer, which can serve as a passivation layer for chips derived from the semiconductor substrate.
Claims33
A method of processing a semiconductor substrate, the method comprising:
- forming a laminate comprising a semiconductor substrate having a conductive region, a polymeric layer, and a release layer, wherein the polymeric layer is disposed between the semiconductor substrate and the release layer;
- forming an aperture in the polymeric layer and the release layer to expose the conductive region;
- depositing a solder composition within the aperture;
- reflowing the solder composition while the solder composition is within the aperture to form a solder bump;
- and
- separating the release layer from the polymeric layer.
3 more elements
A method of forming an electrical assembly comprising:
- forming a laminate comprising (i) a semiconductor substrate having plural chips and plural conductive regions, (ii) a polymeric layer, and (iii) a release layer, wherein the polymeric layer is disposed between the semiconductor substrate and the release layer;
- forming plural apertures in the polymeric layer and the release layer to expose the conductive regions;
- depositing a solder composition within the apertures;
- reflowing the solder composition while the solder composition is within the apertures to form plural solder bumps on the semiconductor substrate;
- separating the release layer from the polymeric layer;
- cutting the semiconductor substrate and the polymeric layer to separate the plurality of chips from each other, wherein at least one chip includes solder bumps and a portion of the polymeric layer disposed on a surface of the at least one chip, and the portion of the polymeric layer is disposed around the solder bumps;
- mounting the at least one chip on a circuit substrate so that solder bumps on the at least one chip are coupled to conductive regions on the circuit substrate.
4 more elements
A method of processing a semiconductor substrate, the method comprising:
- forming a laminate comprising a semiconductor substrate having a conductive region, a polymeric layer, and a release layer, wherein the polymeric layer is disposed between the semiconductor substrate and the release layer;
- forming an aperture in the polymeric layer and the release layer to expose the conductive region, said forming an aperture comprising laser drilling the polymeric layer and the release layer to expose the conductive region;
- depositing a solder composition within the aperture;
- reflowing the solder composition while the solder composition is within the aperture to form a solder bump;
- and
- separating the release layer from the polymeric layer.
3 more elements
A method of processing a semiconductor substrate, the method comprising:
- forming a laminate comprising a semiconductor substrate having a conductive region, a polymeric layer, and a release layer, wherein the polymeric layer is disposed between the semiconductor substrate and the release layer;
- forming an aperture in the polymeric layer and the release layer to expose the conductive region;
- depositing a solder composition within the aperture;
- reflowing the solder composition while the solder composition is within the aperture to form a solder bump having a height which is substantially equal to the thickness of the polymeric layer;
- and
- separating the release layer from the polymeric layer.
3 more elements
A method of forming an electrical assembly comprising:
- forming a laminate comprising (i) a semiconductor substrate having plural chips and plural conductive regions, (ii) a polymeric layer, and (iii) a release layer, wherein the polymeric layer is disposed between the semiconductor substrate and the release layer;
- forming plural apertures in the polymeric layer and the release layer to expose the conductive regions, said forming plural apertures in the polymeric layer and the release layer comprises laser drilling the polymeric layer and the release layer through a laser mask to form the plural apertures;
- depositing a solder composition within the apertures;
- reflowing the solder composition while the solder composition is within the apertures to form plural solder bumps on the semiconductor substrate;
- separating the release layer from the polymeric layer;
- cutting the semiconductor substrate and the polymeric layer to separate the plurality of chips from each other, wherein at least one chip includes solder bumps and a portion of the polymeric layer disposed on a surface of the at least one chip, and the portion of the polymeric layer is disposed around the solder bumps;
- and
- mounting the at least one chip on a circuit substrate so that solder bumps on the at least one chip are coupled to conductive regions on the circuit substrate.
5 more elements
Dependencies are inferred from the claim text.