Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance

A method of forming a MOSFET device having low overlap capacitance and a short channel length comprising the steps of:

• (i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer on said pad oxide layer, and a SiO2 layer formed on said polysilicon layer;
• (ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;
• (iii) removing said SiO2 layer from said patterned dummy gate region;
• (iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;
• (v) forming spacers on sidewalls of said dummy gate region;
• (vi) forming activated source/drain regions in said substrate;
• (vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;
• (viii) forming an insulator layer surrounding said dummy gate region;
• (ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;
• (x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate;
• (xi) forming a high-k, low-temperature metal oxide in said opening;
• and
• (xii) filling said opening with a gate conductor deposited at low temperatures.