Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs

Abstract

Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850° C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850° C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850° C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850° C. gate oxidation step may follow the RTO gate oxidation step.

Dependencies are inferred from the claim text.