Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process

A method of fabricating a damascene, vertical metal-insulator-metal capacitor structure, for embedded dynamic random access memory (DRAM), devices, on a semiconductor substrate, comprising the steps of:

• providing a first level copper interconnect structure, embedded in an insulator layer, with said first level copper interconnect structure overlying and contacting a MOSFET device source/drain region in said semiconductor substrate;
• depositing a first insulator stop layer;
• supplying a first low dielectric constant (low k), insulator layer;
• depositing a second insulator stop layer;
• performing a first anisotropic dry etching procedure to form a first capacitor opening in said second insulator stop layer and in said first low k insulator layer;
• performing an isotropic etch to create a lateral recess in said first low k insulator layer;
• performing a second anisotropic dry etching procedure to remove a portion of said first insulator layer exposed in said first capacitor opening, forming a final capacitor opening, exposing a portion of said first level copper interconnect structure;
• depositing a first conductive layer;
• forming an organic plug structure on a portion of said first conductive layer located in said final capacitor opening;
• performing a third anisotropic dry etching procedure to remove portions of said first conductive layer not covered by said organic plug, forming a bottom electrode structure in said final capacitor opening, with said bottom electrode structure overlying and contacting said first level copper interconnect structure;
• depositing a high dielectric constant (high k), insulator layer;
• depositing a second conductive layer completely filling said final capacitor opening;
• removing portions of said second conductive layer, and portions of said high k insulator layer, from the top portion of said second insulator stop layer, creating said damascene, vertical metal-insulator-metal, capacitor structure in said final capacitor opening, with said damascene, vertical metal-insulator-metal capacitor structure comprised of a top electrode structure formed from said second conductive layer, a capacitor dielectric layer formed from said high k insulator layer, and said underlying bottom electrode structure;
• depositing a second low k insulator layer;
• and
• forming a second level copper interconnect structure in an opening in said second low k insulator layer, with said second level copper interconnect structure overlying and contacting said damascene, vertical metal-insulator-metal capacitor structure.