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US 6,271,075 B1Granted
Method of manufacturing semiconductor device which can reduce manufacturing cost without dropping performance of logic mixed DRAM
AssigneeNEC Corporation
InventorKozo Fukui
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device, includes a providing step, a forming step, and a removing step. The providing step includes providing a DRAM section and a logic section in a substrate. The forming step includes forming a first silicide layer in the DRAM section and a second silicide layer in the logic section. The removing step includes removing the first silicide layer.
Claims23
A method of manufacturing a semiconductor device, comprising:
- (f) providing a DRAM section and a logic section in a substrate;
- (g) forming a first diffusion layer in said DRAM section and a second diffusion layer in said logic section;
- (h) forming a first silicide layer in said first diffusion layer and a second silicide layer in said second diffusion layer;
- (i) removing said first silicide layer to expose said first diffusion layer;
- and
- (j) forming a contact plug such that said contact plug is connected to said exposed first diffusion layer directly.
3 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- providing a DRAM section and a logic section in a substrate;
- forming a first silicide layer in said DRAM section and a second silicide layer in said logic section;
- forming a gate layer in said DRAM section adjacent to said first silicide layer;
- forming side walls on portions of said gate layer that oppose each other across said first silicide layer;
- changing to amorphous a part of said first silicide layer that is exposed between said side walls;
- and
- removing the amorphous part of said first silicide layer.
4 more elements
A method of manufacturing a semiconductor device, comprising the steps of:
- forming a silicide layer in a substrate;
- forming a gate layer adjacent to said silicide layer;
- forming side walls on portions of said gate layer that oppose each other across said silicide layer;
- ion implanting a part of said silicide layer that is exposed between said side walls to change the part to amorphous and reduce the part's etching resistivity;
- and
- etching away the amorphous part of said silicide layer.
3 more elements
Dependencies are inferred from the claim text.