Method of manufacturing a storage node having five polysilicon bars

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising:

• providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures include a node contact region within said semiconductor substrate;
• depositing a first dielectric layer overlying said semiconductor device structures and planarizing said first dielectric layer;
• opening a contact through said first dielectric layer to said node contact region;
• depositing a first layer of polysilicon overlying said first dielectric layer and filling said contact opening wherein said first polysilicon layer has a first thickness overlying said first dielectric layer;
• forming a photoresist mask overlying the portion of said first polysilicon layer over said node contact region;
• silylating said photoresist mask to form a top silylated photoresist portion and silylated photoresist sidewalls on the surfaces of said photoresist mask;
• removing said top silylated photoresist portion;
• removing said photoresist mask whereby said silylated photoresist sidewalls remain;
• etching away a portion of said first polysilicon layer where it is not covered by said silylated photoresist sidewalls using an etching recipe having a high etch selectivity of said silylated photoresist with respect to said polysilicon thereby forming two first polysilicon bars underlying said silylated photoresist sidewalls and leaving a second thickness of said first polysilicon layer overlying said first dielectric layer smaller than said first thickness;
• removing said silylated photoresist sidewalls;
• depositing a second dielectric layer overlying said first polysilicon layer;
• anisotropically etching back said second dielectric layer to form inner spacers on the inner sides of said two first polysilicon bars and outer spacers on the outer sides of said two first polysilicon bars wherein there is a gap between said inner spacers;
• depositing a second polysilicon layer overlying said first polysilicon layer, said first polysilicon bars, and said spacers;
• anisotropically etching back said first and second polysilicon layers to form two second polysilicon bars on the outside edges of said outer spacers and a third second polysilicon bar filling said gap between said inner spacers whereby three second polysilicon bars are formed and to form a T-shaped first polysilicon layer wherein the vertical portion of said T-shape lies within said node contact opening and wherein the horizontal portion of said T-shape overlies said vertical portion and underlies said two first polysilicon bars and said three second polysilicon bars;
• removing said dielectric spacers whereby said T-shaped first polysilicon layer and said two first polysilicon bars and said three second polysilicon bars make five polysilicon bars which together form a storage node of said capacitor;
• depositing a capacitor dielectric layer over said first dielectric layer and said storage node;
• depositing a third polysilicon layer overlying said capacitor dielectric layer wherein said third polysilicon layer forms the top electrode of said capacitor;
• and
• patterning said third polysilicon layer and said capacitor dielectric layer to complete formation of said DRAM with capacitor.